ISL8502 Intersil Corporation, ISL8502 Datasheet - Page 17

• Manufacturer Part Number: ISL8502
• Description: 2.5A Synchronous Buck Regulator
• Manufacturer: Intersil Corporation

For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 36 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
amplifier output (V
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V
PWM wave is smoothed by the output filter (L
The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage DV
incorporates a feed forward loop that accounts for changes
in the input voltage. This maintains a constant modulator
gain.
ΔV
FIGURE 36. VOLTAGE-MODE BUCK CONVERTER
OUT
OSC
) is regulated to the Reference voltage level. The error
V
OUT
OSC
OUT
COMPARATOR
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
=
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
V
0.6
ISL8502
/V
E/A
PWM
E/A
E/A
×
Z
+
-
LC
⎛
⎜
⎝
FB
-
+
COMP
) is compared with the oscillator (OSC)
1
. This function is dominated by a DC
C
+
REFERENCE
and a zero at F
2
REFERENCE
R
------ -
R
C
1
4
O
-
+
⎞
⎟
⎠
1
IN
17
DRIVER
DRIVER
and C
R
Z
2
at the PHASE node. The
IN
OSC
O
FB
Z
), with a double pole
FB
ESR
. The ISL8502
PHASE
R
(PARASITIC)
V
C
4
IN
IN
3
. The DC Gain of
L
Z
R
) divided by the
O
IN
1
O
R
ESR
and C
3
C
O
V
OUT
O
V
).
OUT
ISL8502
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL8502) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. Equation 12 below relates the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
F
F
Figure 37 shows an asymptotic plot of the DC/DC
converter’s gain vs. frequency. The actual Modulator Gain
has a high gain peak due to the high Q factor of the output
filter and is not shown in Figure 37. Using the above
guidelines should give a Compensation Gain similar to the
curve plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at F
with the capabilities of the error amplifier. The Closed Loop
Gain is constructed on the graph of Figure 37 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than +45°.
Include worst case component variations when determining
phase margin. A more detailed explanation of voltage mode
control of a buck regulator can be found in Tech Brief TB417,
titled “Designing Stable Compensation Networks for Single
Phase Voltage Mode Buck Regulators.”
F LC
1. Pick Gain (R
2. Place 1
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Z1
Z2
FB
3
, C
=
=
and Z
=
FB
1
----------------------------------- -
2π x R
------------------------------------------------------ -
2π x R
------------------------------------------ -
2π x
, C
. The goal of the compensation network is to provide
2
IN
ST
, and C
ND
ST
ND
(
0dB
1
to provide a stable, high bandwidth (BW) overall
2
L O x C O
1
1
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero.
x C
Zero at Filter’s Double Pole.
Pole at Half the Switching Frequency.
+
) and adequate phase margin. Phase margin
1
2
R
/R
1
3
3
) x C
) in Figure 38. Use these guidelines for
1
) for desired converter bandwidth.
3
F
F
F ESR
P1
P2
=
=
=
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
------------------------------------------- -
2π x ESR x C O
1
2
3
x
x C
1
1
⎛
⎜
⎝
C
--------------------- -
C
3
1
1
January 17, 2007
+
x C
0dB
C
(EQ. 12)
(EQ. 11)
2
2
LC
FN6389.0
1
⎞
⎟
⎠
P2
, R
IN
and
).
2
,