ISL8502 Intersil Corporation, ISL8502 Datasheet
ISL8502
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ISL8502 Summary of contents
Page 1
... MOSFETs integrated into the IC, the complete regulator footprint can be very small and provide a much more efficient solution than a linear regulator. The ISL8502 is capable of stand alone operation or it can be used in a master slave combination for multiple outputs that are derived from the same input rail. Multiple slave channels (up to six) can be synchronized ...
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Block Diagram PVCC VIN SERIES REGULATOR SGND EN SYNCH CLOCK AND M/S OSCILLATOR GENERATOR FS VCC SS PVCC POR 30μA MONITOR BIAS FAULT MONITORING VOLTAGE MONITOR 0.6V REFERENCE FB COMP PGOOD VIN (x4) OC MONITOR PVCC GATE DRIVE AND ADAPTIVE ...
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... PGOOD VIN EN SYNCH BOOT M/S VCC ISL8502 PVCC PHASE SS PGND FS FB COMP SGND STAND ALONE REGULATOR: V 5.5V TO 14V IN PGOOD VIN EN PVCC BOOT VCC SS ISL8502 PHASE SYNCH PGND M SGND COMP STAND ALONE REGULATOR: V 4. 5.5V to 14V V OUT + V IN 4. OUT + FN6389.0 ...
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... ISL8502 With Multiple Slaved Channels MASTER PVCC M/S VIN SS FS PHASE SYNCH GND ISL8502 ENABLE ISL8502 OUT1 + M/S VIN FS V OUT2 PHASE SYNCH + EN GND ISL8502 SLAVE 5K M/S VIN FS R PHASE SYNCH GND ISL8502 SLAVE January 17, 2007 V OUTN FN6389.0 ...
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... Rising Enable Threshold Voltage Falling Enable Threshold Voltage Enable Sinking Current OSCILLATOR PWM Frequency Ramp Amplitude 5 ISL8502 Thermal Information Thermal Resistance QFN Package (Notes Maximum Junction Temperature (Plastic Package +150° +6.0V Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Maximum Lead Temperature (Soldering 10s +300°C ...
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... PGOOD PGOOD Threshold PGOOD Rising Delay PGOOD Leakage Current PGOOD Low Voltage PGOOD Sinking Current PROTECTION Positive Current Limit Negative Current Limit Undervoltage Level Thermal Shutdown Setpoint Thermal Recovery Setpoint 6 ISL8502 CC SYMBOL TEST CONDITIONS Δ OSC IN V /ΔV By Design VIN ...
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... FIGURE 3. EFFICIENCY vs LOAD (V 100 14V OUTPUT LOAD (A) FIGURE 5. EFFICIENCY vs LOAD (V 7 ISL8502 V = 12V 2.5V 2A 500kHz 4.7µ OUT +25° C, unless otherwise noted 0.6V 500kHz) FIGURE 2. EFFICIENCY vs LOAD (V ...
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... IN 1.814 1.814 1.813 1.813 14V IN 1.812 1.812 1.811 1.811 1.810 0 1 OUTPUT LOAD (A) FIGURE 11. V REGULATION vs LOAD (V OUT 8 ISL8502 V = 12V 2.5V 2A 500kHz 4.7µ OUT +25° C, unless otherwise noted. (Continued) A 0.6026 0.6025 0.6024 0.6023 0.6022 0.6021 0.6020 0.6019 2 0 FIGURE 8 ...
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... OUTPUT LOAD (A) FIGURE 15. POWER DISSIPATION vs LOAD (V 500kHz) 2.5 2.0 1.5 1.0 14V IN 0.5 0 OUTPUT LOAD (A) FIGURE 17. POWER DISSIPATION vs LOAD (V 500kHz) 9 ISL8502 V = 12V 2.5V 2A 500kHz 4.7µ OUT +25° C, unless otherwise noted. (Continued) A 5.030 5.028 5V IN 5.026 5.024 5.022 IN 5.020 2 = 3.3V 500kHz) FIGURE 14. V OUT ...
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... OUTPUT LOAD (A) FIGURE 21. POWER DISSIPATION vs LOAD (V 500kHz) 5.5 5.4 NO LOAD 5.3 5.2 5.1 5.0 4.9 4.8 4.7 4.6 4 (V) IN FIGURE 23. VCC REGULATION ISL8502 V = 12V 2.5V 2A 500kHz 4.7µ OUT +25° C, unless otherwise noted. (Continued) A 2.5 2.0 1.5 1.0 0 0.0 2 FIGURE 20. POWER DISSIPATION vs LOAD (VOUT = 3. ...
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... PHASE1 10V/DIV IL1 1A/DIV FIGURE 27. MASTER OPERATION WITH NEGATIVE LOAD EN1 5V/DIV VOUT1 1V/DIV IL1 1A/DIV SS1 2V/DIV FIGURE 29. SOFT-START AT FULL LOAD 11 ISL8502 V = 12V 2.5V 2A 500kHz 4.7µ OUT +25° C, unless otherwise noted. (Continued) A RIPPLE 20mV/DIV SYNCH1 2V/DIV FIGURE 26. MASTER OPERATION WITH FULL LOAD ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 ISL8502 V = 12V 2.5V 2A 500kHz 4.7µ ...
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... As a slave device, this pin is an input to receive the clock signal from the master device. If configured as a slave device, the ISL8502 will be disabled if there is no clock signal from the master device on the SYNCH pin. ...
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... EN pins tied directly to the enable bus. If the EN pin of an ISL8502 is tied to the enable bus through a diode (anode tied to ISL8502 EN pin, cathode tied to enable bus) then this part will not disable other devices on the enable bus if it disables itself for any reason ...
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... T f kHz OSC If the FS pin is left unconnected, the ISL8502 will default to a 500kHz switching frequency. Output Voltage Selection The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier ...
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... Given a sufficiently fast control loop design, the ISL8502 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level ...
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... ISL8502 Modulator Break Frequency Equations The compensation network consists of the error amplifier (internal to the ISL8502) and the impedance networks Z and Z a closed loop transfer function with the highest 0dB crossing frequency (f is the difference between the closed loop phase at f 180 degrees. Equation 12 below relates the compensation network’ ...
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... There are two sets of critical components in the ISL8502 switching converter. The switching components are the most critical because they switch large amounts of energy, and therefore tend to generate large amounts of noise. Next are the small signal components which connect to sensitive nodes or supply critical bypass current and signal coupling ...
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... Package Outline Drawing L24.4x4D 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/06 4.00 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 19 ISL8502 4X A 20X 24X ± BOTTOM VIEW ± SIDE VIEW ( 20X 24X 24X 0 ...