ISL8104 Intersil Corporation, ISL8104 Datasheet - Page 12

• Manufacturer Part Number: ISL8104
• Description: Synchronous Buck Pulse-Width Modulator (PWM) Controller
• Manufacturer: Intersil Corporation

the switching interval, T
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for
use with the ISL8104. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFETs absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by
a bootstrap circuit from +14V. The boot capacitor, C
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of +12V
less the boot diode drop (V
turns on. A MOSFET can only be used for Q1 if the
MOSFETs absolute gate-to-source voltage rating exceeds
the maximum voltage applied to +14V. For Q2, a logic-level
MOSFET can be used if its absolute gate-to-source voltage
rating also exceeds the maximum voltage applied to +14V.
Figure 10 shows the upper gate drive supplied by a direct
connection to +14V. This option should only be used in
converter systems where the main input voltage is +5VDC or
less. The peak upper gate-to-source voltage is
approximately +14V less the input supply. For +5V main
power and +14VDC for the bias, the gate-to-source voltage
of Q1 is 9V. A logic-level MOSFET is a good choice for Q1
and a logic-level MOSFET can be used for Q2 if its absolute
gate-to-source voltage rating exceeds the maximum voltage
applied to PVCC. This method reduces the number of
required external components, but does not provide for
immunity to phase node ringing during turn on and may
result in lower system efficiency.
P
where: D is the duty cycle = V
P
LOWER
UPPER
T
Fs is the switching frequency.
= I
SW
= I
O
O
is the switching interval, and
2
2
x r
x r
DS(ON)
DS(ON)
SW
x D + 1
x (1 - D)
D
which increases the upper
) when the lower MOSFET, Q2
12
O
2
/ V
Io x V
IN
,
IN
x T
SW
x Fs
BOOT
ISL8104
FIGURE 10. UPPER GATE DRIVE - DIRECT V
Schottky Selection
Rectifier D2 is a clamp that catches the negative inductor
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode must
be a Schottky type to prevent the lossy parasitic MOSFET
body diode from conducting. It is acceptable to omit the diode
and let the body diode of the lower MOSFET clamp the
negative inductor swing, but efficiency could slightly decrease
as a result. The diode's rated reverse breakdown voltage
must be greater than the maximum input voltage.
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
+
+
-
-
ISL8104
ISL8104
+14V
+14V
+
GND
D
GND
V
BOOT
D
PHASE
BOOT
UGATE
LGATE
PGND
BOOT
UGATE
LGATE
PGND
PVCC
PVCC
-
+14V
+14V
C
BOOT
Q1
Q2
Q1
Q2
+1.2V TO +14V
+5V OR LESS
D2
CC
D2
V
NOTE:
V
NOTE:
NOTE:
V
NOTE:
V
G-S
G-S
DRIVE OPTION
G-S
G-S
February 13, 2006
≈
≈
≈
≈
V
V
PVCC
PVCC
CC
CC
FN9257.0
- 5V
- V
D