ISL6608 Intersil Corporation, ISL6608 Datasheet - Page 5

• Manufacturer Part Number: ISL6608
• Description: Synchronous Rectified MOSFET Driver
• Manufacturer: Intersil Corporation

Electrical Specifications
Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to
the gate of high-side power N-Channel MOSFET.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate
drive. Connect the bootstrap capacitor between this pin and
the PHASE pin. The bootstrap capacitor provides the charge
to turn on the upper MOSFET. See the Bootstrap Diode and
Capacitor section under DESCRIPTION for guidance in
choosing the appropriate capacitor value.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
three-state PWM Input section under DESCRIPTION for further
details. Connect this pin to the PWM output of the controller.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin for the IC.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
UG/LG Three-state Propagation Delay
Minimum LG On TIME in DCM (Note 5)
OUTPUT
Upper Drive Source Resistance
Upper Driver Source Current (Note 5)
Upper Drive Sink Resistance
Upper Driver Sink Current (Note 5)
Lower Drive Source Resistance
Lower Driver Source Current (Note 5)
Lower Drive Sink Resistance
Lower Driver Sink Current (Note 5)
PARAMETER
5
Recommended Operating Conditions, Unless Otherwise Noted (Continued)
SYMBOL
t
t
t
t
t
LGMIN
PDHU
PDLU
PDHL
t
PDLL
PTS
R
R
R
R
I
I
I
I
U
U
L
L
U
U
L
L
V
V
V
V
V
500mA Source Current
V
500mA Sink Current
V
500mA Source Current
V
500mA Sink Current
V
VCC
VCC
VCC
VCC
VCC
UGATE-PHASE
UGATE-PHASE
LGATE
LGATE
ISL6608
= 5V, Outputs Unloaded
= 5V, Outputs Unloaded
= 5V, Outputs Unloaded
= 5V, Outputs Unloaded
= 5V, Outputs Unloaded
= 2.5V
= 2.5V
TEST CONDITIONS
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high
quality bypass capacitor from this pin to GND.
FCCM (Pin 7 for SOIC-8, Pin 6 for QFN)
The FCCM pin enables or disables Diode Emulation. When
FCCM is LOW, diode emulation is allowed. Otherwise,
continuous conduction mode is forced (FCCM= Forced
Continuous Conduction Mode). See the Diode Emulation
section under DESCRIPTION for more detail.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET
and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
Thermal Pad (in QFN only)
In the QFN package, the pad underneath the center of the
IC is a thermal substrate. The PCB “thermal land” design
for this exposed die pad should include thermal vias that
drop down and connect to one or more buried copper
plane(s). This combination of vias for vertical heat escape
and buried planes for heat spreading allows the QFN to
achieve its full thermal potential. This pad should be either
grounded or floating, and it should not be connected to
other nodes. Refer to TB389 for design guidelines.
= 2.5V
= 2.5V
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
2.00
2.00
2.00
4.00
400
0.5
35
35
20
20
35
1
1
1
MAX
2.5
2.5
2.5
1.0
-
-
-
-
-
-
-
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
Ω
Α
Ω
Α
Ω
Α
Ω
Α