ISL6327 Intersil Corporation, ISL6327 Datasheet - Page 28

• Manufacturer Part Number: ISL6327
• Description: Enhanced 6-Phase PWM Controller
• Manufacturer: Intersil Corporation

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output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V
peak sawtooth signal amplitude as described in Electrical
Specifications.
Output Filter Design
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must
provide the transient energy until the regulator can respond.
Because it has a low bandwidth compared to the switching
frequency, the output filter necessarily limits the system
transient response. The output capacitor must supply or sink
load current while the current in the output inductors
increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ΔI; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ΔV
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates by an amount:
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor AC ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to I
ΔV
≈
(
ESL
)
---- -
dt
MAX
di
+
C,PP
(
MAX
. Capacitors are characterized according to
ESR
(ESR). Thus, once the output capacitors
.
) ΔI
28
PP
is the peak-to-
(EQ. 37)
ISL6327
are selected, the maximum allowable ripple voltage,
V
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV
Equation 39 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 40
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
Input Supply Voltage Selection
The VCC input of the ISL6327 can be connected either
directly to a +5V supply or through a current limiting resistor
to a +12V supply. An integrated 5.8V shunt regulator
maintains the voltage on the VCC pin when a +12V supply is
used. A 300Ω resistor is suggested for limiting the current
into the VCC pin to a worst-case maximum of approximately
25mA.
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in MOSFETs, and they establish the upper limit for
the switching frequency. The lower limit is established by the
requirement for fast transient response and small output-
voltage ripple as outlined in Output Filter Design. Choose the
lowest switching frequency that allows the regulator to meet
the transient-response requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, R
Typical Application on pages 4 and 5). Equation 3 is
provided to assist in selecting the correct value for R
L
L
L
PP(MAX)
≤
≤
≥
MAX
2NCV
-------------------- - ΔV
(
------------------------- - ΔV
1.25
(
(
ESR
(
ΔI
ΔI
. This places an upper limit on inductance.
)
) NC
2
)
O
2
)
, determines the lower limit on the inductance.
⎛
⎝
----------------------------------------------------------- -
V
IN
f
S
MAX
V
–
MAX
IN
N V
V
–
OUT
PP MAX
ΔI ESR
–
ΔI ESR
(
(
(
⎞ V
⎠
OUT
)
T
)
)
(see the figures labelled
⎛
⎝
V
IN
–
V
O
⎞
⎠
June 5, 2006
T
(EQ. 38)
(EQ. 39)
(EQ. 40)
.
FN9276.1