PBL38640-2 Ericsson, PBL38640-2 Datasheet - Page 13

• Manufacturer Part Number: PBL38640-2
• Description: Subscriber Line Interface Circuit
• Manufacturer: Ericsson

Figure 12. Single-channel subscriber line interface with PBL 386 40/2 and combination CODEC/filter.
and AGND, the overhead voltage can be
set to higher values, typical values can
be seen in figure 11. The R
corresponding V
are typical values for THD <1% and the
signal frequency 1000Hz.
V
So if the gain 2-wire to 4-wire is 0dB,
side. Signal levels between 3,2 and
6,4 V
handled with the PTG shorted so that the
gain G
that the 2-wire impedance, R
4-wire to 4-wire gain has to be recalcu-
lated if the PTG is shorted.
3,2 V
TX
Observe that the 4-wire output terminal
RESISTORS: (Values according to IEC E96 series)
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
can not handle more than 3,2 V
SG
LD
OV
LC
REF
R
T
TX
B
RX
FB
1
2
3
4
RT
P1
F1
, R
Peak
, R
Peak
2-4S
P2
F2
VB2
on the 2-wire side can be
VB
is maximum also for the 2-wire
+12 V /+5V
become -6,02dB. Please note
D
RING
VB
D
TIP
= 0
= 49.9 k
= User programmable
= 32.4 k
= 49.9 k
= 64.9 k
= 105 k
= 24.9 k
= 22.1 k
= 52.3 k
Depending on CODEC / filter
= 604 k
= 604 k
= 249 k
= 280 k
= 330
= 10
= Line resistor, 40
BB
TRO
K
R
D
VB2
C
C
VB
(signal headroom)
VB2
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
1% 1/10 W
5% 2 W
1% 1/10 W (Note 1)
OV
R
R
R
E
RT
F2
F1
RG
R
and
and the
1% match
R
R
Peak.
C
OVP
1
2
GG
C
1
VB
R
R
P2
P1
current at the 2-wire side can not be
greater than 9 mA.
How to use POV:
1. Decide what overhead voltage(V
2. In figure 11 the corresponding R
3. If the overhead voltage exceeds
Please note that the maximum signal
D
R
HP
3
CAPACITORS: (Values according to IEC E96
series)
C
C
C
C
C
C
C
C
C
C
C
is needed. The POV function is only
needed if the overhead voltage
exceeds 3,2 V
the decided V
3,2 V
changed to -6,02dB by connecting
the PTG pin to AGND. Please note
that the two-wire impedance, R
the 4-wire to 4-wire gain has to be
recalculated.
VB
VB2
VCC
TC
RC
HP
LP
TX
GG
1
2
R
4
Peak
C
SLIC No. 2 etc.
C
C
2
R
RC
TC
SG
C
C
LP
, the G
HP
= 100 nF
= 150 nF
= 100 nF
= 2.2 nF
= 2.2 nF
= 47 nF
= 150 nF
= 100 nF
= 220 nF
= 330 nF
= 330 nF
PTG
RRLY
RINGX
BGND
TIPX
VBAT
VBAT2
PSG
PBL 386 40/2
HP
NC
NC
LP
DT
DR
TRO
Peak
2-4S
can be found.
gain has to be
100 V 10%
100 V 10%
100 V 10%
100 V 10%
100 V 10%
100 V 10%
100 V 10%
10 V 10%
10 V 10%
63 V 10%
63 V 10%
AGND
RSN
POV
VCC
VTX
REF
PLC
PLD
DET
NC
NC
C1
C2
C3
SYSTEM CONTROL
VCC
R
R
R
R
REF
LC
OV
LD
INTERFACE
R
OV
TRO
and
R
for
R
T
)
R
C
TX
Analog Temperature Guard
The widely varying environmental
conditions in which SLICs operate may
lead to the chip temperature limitations
being exceeded. The PBL 386 40/2 SLIC
reduce the dc line current when approxi-
mately 145 C and increases it again
automatically when the temperature
drops. Accordingly transmission is not
lost under high ambient temperature
conditions.
a logic low level when the temperature
guard is active.
R
R
NOTES:
1. R
2. It is required to connect D
DIODES:
D
D
D
D
OVP:
Secondary protection (e.g. Power
Innovations TISPPBL2). The ground
terminals of the secondary protection should
be connected to the common ground on the
Printed Board Assembly with a track as
short and wide as possible, preferable a
groundplane.
The detector output, DET, is forced to
TX
RX
VB
VB2
BB
HP
HP and ground if C
C
VCC
P1
PBL 386 40/2
and R
R
B
P2
= 1N4448
= 1N4448
= 1N4448
= 1N4448 (Note 2)
may be omitted if D
R
CODEC/
-
+
VCC
-
+
0
FB
Filter
0
HP
PBL 386 40/2
> 47nF
HP
between terminal
VB
is in place.
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