PBL38640-2 Ericsson, PBL38640-2 Datasheet

PBL38640-2

Manufacturer Part Number

PBL38640-2

Description

Subscriber Line Interface Circuit

Manufacturer

Ericsson

Datasheet

1.PBL38640-2.pdf (16 pages)

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Description

The PBL 386 40/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated

circuit for use in Digital Loop Carrier, FITL and other telecommunications equipment.

The PBL 386 40/2 has been optimized for low total line interface cost and a high

degree of flexibility in different applications.

and 2x900 , with short loop current limiting adjustable to max 45 mA. In the current

limited region the loop feed is nearly constant current with a slight slope correspond-

ing to 2x30 k .

loop power dissipation. The SLIC automatically switches between the two battery

supply voltages without need for external components or external control.

The PBL 386 40/2 is compatible with both loop and ground start signaling.

accomplished by the SLIC in conjunction with either a conventional CODEC/filter or

with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable

two-wire impedance, complex or real, is set by a simple external network.

longitudinal balance specifications meet the DLC requirements.

28-pin PLCC.

Figure 1. Block diagram.

The PBL 386 40/2 emulates resistive loop feed, programmable between 2x50

A second, lower battery voltage may be connected to the device to reduce short

The SLIC incorporates loop current, ground key and ring trip detection functions.

Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is

Longitudinal voltages are suppressed by a feedback loop in the SLIC and the

The PBL 386 40/2 package options are 24-pin SSOP package, 24-pin SOIC and

RINGX

VBAT2

AGND

BGND

VBAT

TIPX

VCC

Two-wire

Interface

Transmission

Suppression

Comparator

Longitudinal

Ground Key

Line Feed

Controller

VF Signal

Ring Trip

Off-hook

Detector

Signal

and

PTG

Ring Relay

Decoder

Control

Driver

Input

and

PLC

PLD

REF

VTX

RSN

DET

POV

PSG

RRLY

Interface Circuit

Subscriber Line

Key Features

• 24-pin SSOP package

• High and low battery with automatic

• 65 mW on-hook power dissipation in

• On-hook transmission

• Long loop battery feed tracks Vbat for

• Only +5 V feed in addition to battery

• Selectable transmit gain (1x or 0.5x)

• No power-up sequence

• Programmable signal headroom

• 43V open loop voltage @ -48V battery

• Constant loop voltage for line leakage

• Full longitudinal current capability

• Analog over temperature protection

• Line voltage measurement

• Polarity reversal

• Ground key detector

• Tip open state with ring ground

• -40 C to +85 C ambient temperature

switching

active state

maximum line voltage

feed

<5 mA (RLeak ~ >10 k @ -48V)

during on-hook state

permits transmission while the

protection circuit is active

detector

range

PBL 386 40/2

24-pin SOIC, 24-pin SSOP, 28-pin PLCC

March 2000

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