BD9120HFN Rohm, BD9120HFN Datasheet - Page 33

• Manufacturer Part Number: BD9120HFN
• Description: (BD9106FVM - BD9120HFN) Synchronous Buck Converter Integrated FET
• Manufacturer: Rohm

BD9106FVM BD9107FVM BD9109FVM BD9110NV BD9120HFN
© 2012 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
www.rohm.com
4. Determination of RITH, CITH that works as a phase compensator
5. Determination of output voltage
Phase
Phase
V
Gain
[deg]
Gain
[deg]
[dB]
[dB]
CC
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
The output voltage V
V
With R1 and R2 adjusted, the output voltage may be determined as required.
Use 1 kΩ to 100 kΩ resistor for R1. If a resistor of the resistance higher than
100 kΩ is used, check the assembled set carefully for ripple voltage etc.
Adjustable output voltage range： 1.0V to 1.5V/ BD9107FVM, BD9120HFN
OUT
-90
-90
Fig.100 Error amp phase compensation characteristics
A
A
0
0
0
0
=(R2/R1+1)×V
fz
Fig.99 Open loop gain characteristics
(Amp.)
V
Cin
R
C
OUT
ITH
ITH
= fp
I
2π×R
Fig.101 Typical application
OUT
fp(Min.)
fz(Amp.)
(Min.)
Min.
EN
V
ITH
ITH
ADJ
OUT
OUT
1
fp(Max.)
×C
・・・(7) V
is determined by the equation (7):
I
ITH
OUT
V
GND,PGND
CC
Max.
,PV
1.0V to 2.5V/BD106FVM, BD9110NV
CC
=
fz(ESR)
ADJ
SW
2π×R
: Voltage at ADJ terminal (0.8V Typ.)
OMax.
L
ESR
C
1
O
×C
O
33/40
Pole at power amplifier
Zero at power amplifier
fp=
fz
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
Increasing capacitance of the output capacitor lowers the
pole frequency while the zero frequency does not change.
(This is because when the capacitance is doubled, the
capacitor ESR reduces to half.)
R
(ESR)
O
www.DataSheet.co.kr
2π×R
V
=
OUT
2π×E
1
O
fp
fp
fz
×C
(Amp.)
(Min.)
(Max.)
SR
O
1
×C
=
=
=
O
2π×R
2π×R
2π×R
Fig.102 Determination of output voltage
SW
ADJ
OMax.
OMin.
ITH.
1
1
1
×C
TSZ02201-0J3J0AJ00090-1-2
×C
×C
ITH
O
O
L
02.MAR.2012 Rev.001
[Hz]←with lighter load
[Hz]←with heavier load
Co
Datasheet
R2
R1
Output
Datasheet pdf - http://www.DataSheet4U.net/