MC145170-1 Motorola, MC145170-1 Datasheet - Page 8

• Manufacturer Part Number: MC145170-1
• Description: PLL FREQUENCY SYNTHESIZER WITH SERIAL INTERFACE
• Manufacturer: Motorola

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DIGITAL INTERFACE PINS
D in
Serial Data Input (Pin 5)
and is shifted in on the low–to–high transition of CLK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the N register, or 3 bytes
(24 bits) to access the R register. Additionally, the R register
can be accessed with a 15–bit transfer (see Table 1). An op-
tional pattern which resets the device is shown in Figure 13.
The values in the C, N, and R registers do not change during
shifting because the transfer of data to the registers is con-
trolled by ENB.
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the three registers.
Random access of any register is provided (i.e., the registers
may be accessed in any sequence). Data is retained in the
registers over a supply range of 2.5 to 5.5 V. The formats are
shown in Figures 13, 14, 15, and 16.
immunity. This input can be directly interfaced to CMOS de-
vices with outputs guaranteed to switch near rail–to–rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 to
10 k must be used. Parameters to consider when sizing the
resistor are worst–case I OL of the driving device, maximum
tolerable power consumption, and maximum data rate.
CLK
Serial Data Clock Input (Pin 7)
while high–to–low transitions shift bits from D out . The chip’s
16–1/2–stage shift register is static, allowing clock rates
down to dc in a continuous or intermittent mode.
to reset the device; this is optional. Eight clock cycles are re-
quired to access the C register. Sixteen clock cycles are
needed for the N register. Either 15 or 24 cycles can be used
to access the R register (see Table 1 and Figures 13, 14, 15,
and 16). For cascaded devices, see Figures 24 — 31.
Schmitt–triggered input buffer. Slow CLK rise and fall times
are allowed. See the last paragraph of D in for more informa-
tion.
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The bit stream begins with the most significant bit (MSB)
The bit stream needs neither address nor steering bits due
D in typically switches near 50% of V DD to maximize noise
Low–to–high transitions on Clock shift bits available at D in ,
Four clock cycles followed by five clock cycles are needed
CLK typically switches near 50% of V DD and has a
Values > 32
of Clocks
(MSBs are shifted in first, C0, N0, and R0 are the LSBs)
Number
15 or 24
4 + 5
16
8
32
Table 1. Register Access
PIN DESCRIPTIONS
See Figures
Accessed
C Register
N Register
R Register
Register
24 — 31
(Reset)
None
N15, N14, N13, . . ., N0
R14, R13, R12, . . ., R0
C7, C6, C5, . . ., C0
Nomenclature
Bit
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ENB
Active–Low Enable Input (Pin 6)
transfer of data to/from the device. When ENB is in an inac-
tive high state, shifting is inhibited, D out is forced to the high–
impedance state, and the port is held in the initialized state.
To transfer data to the device, ENB (which must start inactive
high) is taken low, a serial transfer is made via D in and CLK,
and ENB is taken back high. The low–to–high transition on
ENB transfers data to the C, N, or R register depending on
the data stream length per Table 1.
50% of V DD , thereby minimizing the chance of loading erro-
neous data into the registers. See the last paragraph of D in
for more information.
D out
Three–State Serial Data Output (Pin 8)
through D out on the high–to–low transition of CLK. This out-
put is a No Connect, unless used in one of the manners dis-
cussed below.
around test of serial data. This could be part of a system
check conducted at power up to test the integrity of the sys-
tem’s processor, PC board traces, solder joints, etc.
board manufacturing.
mits cascading devices.
REFERENCE PINS
OSC in /OSC out
Reference Oscillator Input/Output (Pins 1, 2)
terminals of an external parallel–resonant crystal. Fre-
quency–setting capacitors of appropriate values as recom-
mended by the crystal supplier are connected from each pin
to ground (up to a maximum of 30 pF each, including stray
capacitance). An external feedback resistor of 1 to 15 M
connected directly across the pins to ensure linear operation
of the amplifier. The required connections for the compo-
nents are shown in Figure 9.
This pin is used to activate the serial interface to allow the
This input is also Schmitt–triggered and switches near
Data is transferred out of the 16–1/2–stage shift register
D out could be fed back to an MCU/MPU to perform a wrap–
The pin could be monitored at an in–line QA test during
Finally, D out facilitates troubleshooting a system and per-
These pins form a reference oscillator when connected to
To guarantee proper operation of the power–on
reset (POR) circuit, the CLK pin must be held at
the potential of either the V SS or V DD pin during
power up. That is, the CLK input should not be
floated or toggled while the V DD pin is ramping
from 0 to at least 2.5 V. If control of the CLK pin is
not practical during power up, the initialization se-
quence shown in Figure 13 must be used.
Transitions on ENB must not be attempted while
CLK is high. This puts the device out of synchro-
nization with the microcontroller. Resynchroniza-
tion occurs when ENB is high and CLK is low.
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NOTE
NOTE
MOTOROLA
is