MC145170-1 Motorola, MC145170-1 Datasheet - Page 11

• Manufacturer Part Number: MC145170-1
• Description: PLL FREQUENCY SYNTHESIZER WITH SERIAL INTERFACE
• Manufacturer: Motorola

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C4 – C2, OSC2 – OSC0: Reference output controls which determine the REF out characteristics as shown below. Upon
C6 — PDA/B:
C7 — POL:
C5 — LDE:
C0 — f R E:
C1 — f V E:
ENB
* At this point, the new byte is transferred to the C register and stored. No other registers
CLK
D in
are affected.
Figure 14. C Register Access and Format (8 Clock Cycles are Used)
Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts
PD out and interchanges the R function with V as depicted in Figure 17. Also see the phase
detector output pin descriptions for more information. This bit is cleared low at power up.
Selects which phase/frequency detector is to be used. When set high, enables the output of
phase/frequency detector A (PD out ) and disables phase/frequency detector B by forcing R
and V to the static high state. When cleared low, phase/frequency detector B is enabled ( R
and V ) and phase/frequency detector A is disabled with PD out forced to the high–impedance
state. This bit is cleared low at power up.
Enables the lock detector output when set high. When the bit is cleared low, the LD output is
forced to a static low level. This bit is cleared low at power up.
power up, the bits are initialized such that OSC in /8 is selected.
Enables the f V output when set high. When cleared low, the f V output is forced to a static low
level. The bit is cleared low upon power up.
Enables the f R output when set high. When cleared low, the f R output is forced to a static low
level. The bit is cleared low upon power up.
C4
MSB
0
0
0
0
1
1
1
1
C7
1
C6
C3
0
0
1
1
0
0
1
1
2
C5
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C2
3
0
1
0
1
0
1
0
1
C4
4
REF out Frequency
dc (Static Low)
OSC in
OSC in /2
OSC in /4
OSC in /8
OSC in /16
OSC in /8
OSC in /16
C3
5
C2
6
C1
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7
LSB
C0
8
*
MC145170–1
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