MC1151A PMD, MC1151A Datasheet - Page 15

• Manufacturer Part Number: MC1151A
• Description: (MC1x51A) Advanced Step Motor Control Chipset
• Manufacturer: PMD

IC
CP
CP
CP
CP
CP
CP
CP
CP
CP
CP
Pin Name
NegLimit1
NegLimit2
NegLimit3
NegLimit4
ClkIn
ClkOut
~Reset
I/OCntrl0
I/OCntrl1
I/OCntrl2
I/OCntrl3
Data2
Data3
Data4
Data5
Data6
Data7
Data8
Data9
Data10
Data11
I/OAddr0
I/OAddr1
I/OAddr2
I/OAddr3
I/OWrite
Vcc
GND
Pin #
51
44
41
37
24
19
17
16
18
68
67
58
57
50
49
46
43
40
39
36
35
28
9
6
5
15
4, 22, 33
3, 34
Description/Functionality
Negative limit switch input for axis 1-4. These signals provide directional limit inputs for the
negative-side travel limit of the axis. Upon powerup these signals default to "active high"
interpretation, but the interpretation can be set explicitly using the SET_LMT_SENSE
command. If not used these signals should be tied low for the default interpretation, or tied
high if the interpretation is reversed.
NOTE: For MC1451A all 4 pins are valid. For MC1251A pins for axes 1 & 2 only are valid.
For MC1151A pin for axis 1 only is valid. Invalid axis pins can be left un connected.
Clock In (input). This pin provides the chip set master clock (Fclk = 25.0 Mhz)
Clock Out (output). This pin provides a clock output which is 1/4 the ClkIn frequency. This pin
is connected to the CPClk signals of the I/O chip and ENC chip
Master chip set reset (input). When brought low, this pin resets the chip set to its initial
condition. Reset should occur no less than 250 mSec after stable power has been provided
to the chip set.
The master reset signal should be connected to this pin as well as the ~CPReset pin of the
I/O chip
I/O and ENC chip to CP chip communication control (mixed). These signals provide various
inter-chip control signals for the I/O and ENC chips. For the I/O chip these four signals are
connected to the corresponding CPCntrl0-3 pins. For the ENC chip only I/OCntrl0 is used
which is connected to the CPCntrl0 pin.
CP to I/O and ENC chip Data4-11. (Bi-directional). These pins are connected to the
corresponding CPData4-11 pins on the I/O chip, and on the corresponding CPData2-11 pins
on the ENC chip. These signals are used to communicate between the CP and the I/O and
ENC chips.
Address0-3 (output). These signals provide various inter-chip address control signals for the
I/O and ENC chips. For the I/O chip these four signals are connected to the corresponding
CPAddr0-3 pins. For the ENC chip only I/OAddr0, I/OAddr2, and I/OAddr3 are used and they
are connected to the corresponding pins on the ENC chip.
Write (output). This pin is connected to CPWrite on the I/O and on the ENC chip. It provides a
control signal to the I/O and ENC chip to facilitate communication between these chips and
the CP chip
CP chip supply voltage pin. All of these pins must be connected to the supply voltage. Supply
voltage = 4.75 to 5,.25 V
CP chip ground pin. All of these pins must be connected to the power supply return.
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