MC100LVEL34 ON Semiconductor, MC100LVEL34 Datasheet - Page 5

• Manufacturer Part Number: MC100LVEL34
• Description: Clock Generation Chip
• Manufacturer: ON Semiconductor

CLK
CLK
OUTPUT
MR
MR
EN
EN
Q0
Q1
Q2
Q0
Q1
Q2
CLOCK
There are two distinct functional relationships between the Master Reset and Clock:
The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal
divider flip−flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge
of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase rela-
tionships.
MR
T
RR
CASE 2: If the MR is deasserted (H−L), after the Clock has transitioned low, the
CASE 1
CASE 1: If the MR is deasserted (H−L), while the Clock is still high, the
outputs will follow the second ensuing clock rising edge.
outputs will follow the third ensuing clock rising edge.
Figure 3. Reset Recovery Time
Figure 2. Timing Diagrams
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OUTPUT
CLOCK
5
MR
T
RR
Internal Clock
Internal Clock
Disabled
Disabled
CASE 2
Internal Clock
Internal Clock
Enabled
Enabled