MC100LVEL34 ON Semiconductor, MC100LVEL34 Datasheet - Page 2

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MC100LVEL34

Manufacturer Part Number
MC100LVEL34
Description
Clock Generation Chip
Manufacturer
ON Semiconductor
Datasheet

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V
V
Q0
Q0
Q1
Q1
Q2
Q2
CC
CC
Figure 1. 16−Lead Pinout (Top View) and Logic Diagram
Warning: All V
to Power Supply to guarantee proper operation.
1
2
3
4
5
6
7
8
CC
Table 3. ATTRIBUTES
1. For additional information, see Application Note AND8003/D.
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
and V
Q
Q
Q
R
R
R
EE
÷2
÷4
÷8
pins must be externally connected
Q
Characteristics
R
D
http://onsemi.com
16
15
14
13
12
11
10
9
Oxygen Index: 28 to 34
Charged Device Model
Human Body Model
V
EN
NC
CLK
CLK
V
MR
V
CC
BB
EE
Machine Model
2
TSSOP−16
SOIC−16
* Pins will default LOW when left open.
***Pins will default to V
Table 1. PIN DESCRIPTION
Z = Low-to-High Transition
ZZ = High-to-Low Transition
Table 2. FUNCTION TABLE
PIN
CLK*, CLK**
EN*
MR*
Q0, Q0
Q1, Q1
Q2, Q2
V
V
V
NC
CLK
BB
CC
EE
ZZ
Z
X
Pb Pkg
Level 1
Level 1
UL 94 V−0 @ 0.125 in
EN
210 Devices
H
X
L
37.5 kW
> 200 V
> 2 kV
> 2 kV
Value
75 kW
FUNCTION
ECL Diff Clock Inputs
ECL Sync Enable
ECL Master Reset
ECL Diff ÷2 Outputs
ECL Diff ÷4 Outputs
ECL Diff ÷8 Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
CC
Pb−Free Pkg
/2 when left open.
MR
Level 1
Level 1
H
L
L
FUNCTION
Reset Q
Hold Q
Divide
0−3
0−3

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