P4022 EM Microelectronic, P4022 Datasheet - Page 9

• Manufacturer Part Number: P4022
• Description: Multi Frequency Contactless Identification Device
• Manufacturer: EM Microelectronic

LOGIC block
Depending on the state of the SI input at power-
up, the P4022 either enters a test mode (SI = 1) or
its normal operating mode (SI = 0). The SI pin is
internally pulled down, so that it can be left open
for normal operation.
After the power-on reset has disappeared, the chip
boots by reading the SEED and CTL ROMs.
The chip then enters its normal operating mode,
which basically consists of clocking a 16 bit timer
counter with the bit rate clock until it compares
with the number in the random number generator.
At this point a code is transmitted with the correct
preamble at the correct data rate and encoded
correctly. The
clocked to generate a new pseudo random
number, and the 16 bit counter is reset to start a
new delay.
GAP Detection Algorithm
The GAP detection logic contains two main
controllers, one for detecting the ACK signal, and
one for detecting the MUTE and WAKE-UP
signals. The WAKE-UP signal is also called an
asynchronous ACK, as it is really an ACK meant
for another chip. It also contains a pre-processor
for low frequency GAP signals.
Refer to the timing diagrams in Figure 5 and 6 for
the following detailed description of the GAP
detection algorithms.
random number generator
EM MICROELECTRONIC-MARIN SA
HF ACK
LF ACK
Clock
Figure 5: ACK timing diagram
Data
Bit n
ACK timing
T
1
is
The width of the comparison between the 16 bit
random number and the 16 bit delay count
determines the maximum possible delay between
transmissions (reading rate).
maximum delay settings can be pre-programmed.
can be modified by the reception of GAP (MUTE
and ACK) signals, if these are enabled by the CTL
bits.
If an ACK signal is received after transmission of a
code, the chip either turns itself off completely or
reduces the rate at which the delay counter is
clocked, thereby slowing down the rate at which
codes are transmitted.
If a MUTE signal is received while the chip is not
transmitting, the current operation of the chip is
interrupted for 128 clock periods, after which it
continues normally. Reception of more MUTEs
during the sleep state restarts the sleep state. The
sleep state is also terminated by the reception of a
WAKE-UP signal (an ACK signal to a chip which
has just completed transmitting).
ACK
The controller checks for a LOW 1.75 bit periods
after the last bit of code has been transmitted. It
then checks for a HIGH 3 bits later, a LOW 3 bits
later and finally a HIGH a further 3 bits later.
The reader should synchronise itself to
frequency of the received code, check the CRC
and then send two GAPs so that the above pattern
is matched. Ideally to achieve the lowest error
rate, the GAPS should be as narrow as possible
and situated 4.75 and 7.75 bits after the last bit of
code. In practice allowance must be made for
the fact that the on-chip oscillator can drift in the
The basic free-running mode as described above
T
1
P4022
PRELIMINARY
Any one of eight
the
9