P123-09H PhaseLink Corp., P123-09H Datasheet - Page 2

• Manufacturer Part Number: P123-09H
• Description: Low Skew Zero Delay Buffer
• Manufacturer: PhaseLink Corp.

PIN DESCRIPTIONS
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION FOR PL123-09
INPUT / OUTPUT SKEW CONTROL
The PL123-05/-09 will achieve Zero Delay from input to output when all the outputs are loaded equally. Adjust-
ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact PhaseLink for more information.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 4/9/08 Page 2
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
S1
CLKB3
CLKB4
CLKA3
CLKA4
CLKOUT
S2
[3]
[3]
0
0
1
1
Name
[1]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
S1
0
1
0
1
TSSOP-16L
CLOCK A1–A4
4,13
5,12
Three-state
10
11
14
15
16
(Bank A)
1
2
3
6
7
8
9
Driven
Driven
Driven
PL123-09
SOP-16L
4,13
5,12
10
11
14
15
16
1
2
3
6
7
8
9
CLOCK B1–B4
Three-state
Three-state
(Bank B)
Driven
Driven
PL123-05
SOP-8L
1
3
2
6
4
5
7
8
-
-
-
-
-
-
CLKOUT
Driven
Driven
Driven
Driven
Type
O
O
O
O
O
O
O
O
O
P
P
I
I
I
Low Skew Zero Delay Buffer
(Preliminary)
Input reference frequency.
Buffered clock output, Bank A
Buffered clock output, Bank A
VDD connection
GND connection
Buffered clock output, Bank B
Buffered clock output, Bank B
Selector input
Selector input
Buffered clock output, Bank B
Buffered clock output, Bank B
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output. Internal feedback
on this pin.
Output Source
Reference
PLL
PLL
PLL
Description
PLL Shutdown
N
N
Y
N