MT8972B Mitel Networks Corporation, MT8972B Datasheet - Page 3

• Manufacturer Part Number: MT8972B
• Description: (MT8971B) ISO2-CMOS ST-BUS FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit
• Manufacturer: Mitel Networks Corporation

Pin Description (continued)
DIP PLCC
17
18
19
20
21
22
DSTo
DSTo
DSTi
DSTi
F0o
F0o
Pin #
C4
F0
C4
F0
1,6,
11,
18,
20,
22
23
25
24
26
27
28
AAAA
AAAAA
AA AA
AAAA
AAAA
AA AA
AAAA
AAAA
AA AA
AAAA
AAAA A A
AAAA
AAAA
AAAA AA AA
A
AAAA
AAAA
A A
AAAA
AAAA
A A
AAAA
AAAA
AAAA A A
A A
AAAA
AAAA
AAAA
AAAAA
A
AAAA
A A
AAAA
AAAA
A A
AAAA
AAAA
AAAAA
A
AAAA
AAAAA
A
AAAA
A A
AAAA
AAAA
A A
AAAA
AAAA
AAAA A A
A A
AAAA
A A
A
A A
A A
A A
A A
A A
A A
AA
AA AA
A A
AA AA
A
A A
AA AA
A A
A
A A
A A
A A
A A
A
A
A
A A
A A
A A
A A
A
A A
L
B1
B1
Precan
OUT
OSC1
B1
B1
TEST
Name
7
7
V
NC
L
7
7
DD
IN
B1
B1
DIS L
6
6
B1
B1
B1
B1
Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C. Electrical
Characteristics for OSC1 input requirements.
Precanceller Disable. When held to Logic ’1’
precanceller is forced to V
L
k ) is provided on this pin.
No Connection. Leave open circuit.
“0”, L
Test Pin.
Receive Signal input (Analog).
Positive Power Supply (+5V) input.
Channel Time 0
6
6
5
5
OUT
OUT
B1
B1
4
4
B1
B1
to the precanceller path is enabled and functions normally. An internal pulldown (50
OUT
Disable. When held to logic “1”, L
B1
B1
5
5
functions normally. An internal pulldown (50 k ) is provided on this pin.
Channel Time 0
3
3
Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6)
Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)
Connect to V
B1
B1
B1
B1
2
2
4
4
B1
B1
1
1
B1
B1
B1
B1
3
3
0
0
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
SS
Bias
B1
B1
for normal operation.
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
2
2
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
thus bypassing the precanceller section. When logic ’0’, the
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
AAA
B1
B1
B2
B2
1
1
Description
7
7
OUT
B2
B2
B1
B1
is disabled (i.e., output = V
6
6
0
0
B2
B2
,
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
the internal path from L
Channel Time 16
5
5
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
B2
B2
4
4
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
B2
B2
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
3
3
B2
B2
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
2
2
MT8971B/72B
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
B2
B2
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
1
1
B2
B2
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
Bias
OUT
0
0
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
). When logic
to the
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A
A A
A A
A
A A
A A
A
A
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
AAAA
A A
A A
A A
B1
B1
A
A A
A A
A A
B1
B1
9-109
7
7
7
7