MT8972B Mitel Networks Corporation, MT8972B Datasheet - Page 14

• Manufacturer Part Number: MT8972B
• Description: (MT8971B) ISO2-CMOS ST-BUS FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit
• Manufacturer: Mitel Networks Corporation

MT8971B/72B
Applications
Typical connection diagrams are shown in Figures
13 and 14 for the DN mode as a MASTER and
SLAVE, respectively. L
coupling transformer through a resistor R2 and
capacitors
characteristic impedance. Suggested values of R2,
C2 and C2’ for 80 and 160 kbit/s operation are
provided in
protection is provided by R1, D1 and D2. C1 is
present to properly bias the received line signal for
the L
couple to the line with a secondary center tap for
optional phantom power feed. Varistors have been
shown for surge protection against such things as
lightning strikes.
9-120
+5V
CD Port ST-BUS
DV Port ST-BUS
+5V
CD Port ST-BUS
DV Port ST-BUS
Master Clocks
Mode Select
IN
Master Clocks
Mode Select
Lines
input. A 2:1 coupling transformer is used to
Lines
0.33 F
0.33 F
C2
0.33 F
0.33 F
Figures 13 and
{
{
{
{
{
{
and
Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s
Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s
DSTi
DSTo
CDSTi
CDSTo
F0
C4
MS0
MS1
MS2
V
V
C2’
OUT
Ref
Bias
DSTi
DSTo
CDSTi
CDSTo
F0
C4
MS0
MS1
MS2
V
V
MT8971B/72B
MT8971B/72B
Ref
Bias
is connected to the
to
OSC1
OSC2
L
match
OSC1
OSC2
14. Overvoltage
OUT
L
L
OUT
F0o
IN
L
To Next DNIC
IN
the
NC
R2 = 390
R1 = 47
R2 = 390
R1 = 47
10.24 MHz XTAL
C3=33pF=C4
D.C. coupled,
Frequency locked
10.24 MHz clock.
Refer to AC Electrical
Characteristics
DN Mode
Clock Timing
C2’ = 1.5 nF
line
C2’ = 1.5 nF
C2 = 22 nF
C2 = 22 nF
If the scramblers power up with all zeros in them,
they are not capable of randomizing all-zeros data
sequence. This increases the correlation between
the transmit and receive data which may cause loss
of convergence in the echo canceller and high bit
error rates.
In DN mode the insertion of the SYNC pattern will
provide enough pseudo-random activity to maintain
convergence. In MOD mode the SYNC pattern is not
inserted. For this reason, at least one ”1” must be fed
into the DNIC on power up to ensure that the
scramblers will randomize any subsequent all-zeros
sequence.
C1 = 0.33 F
Note: Low leakage diodes (1 & 2) are required so
D2
that the DC voltage at L
+5V
Note: Low leakage diodes (1 & 2) are required so
that the DC voltage at L
D1 = D2 = MUR405
+5V
D1 = D2 = MUR405
D2
2:1
2 : 1
C1 = 0.33 F
1.0 F
1.0 F
IN
IN
For 80 kbit/s: C2’ = 3.3 nF
For 80 kbit/s: C2’ = 3.3 nF
Line Feed
Voltage
V
V
Bias
Bias
Supply
68 Volts
(Typ)
2.5 Joules
0.02 Watt
68 Volts
(Typ)
2.5 Joules
0.02 Watt