MT8885 Mitel Networks Corporation, MT8885 Datasheet - Page 9

• Manufacturer Part Number: MT8885
• Description: Integrated DTMFTransceiver with Power Down & Adaptive Micro Interface
• Manufacturer: Mitel Networks Corporation

Advance Information
(DS). When DS is low, Motorola processor operation
is selected.
Figure 17 shows the timing diagram for the Motorola
MC68HC11 (1 MHz) microcontroller. The chip select
(CS) input is formed by NANDing address strobe
(AS) and address decode output. Again, the MT8885
examines the state of DS on the falling edge of CS to
determine if the micro has a Motorola bus (when DS
is
TMS370CX5X is qualified to have a Motorola
interface. Figure 12(a) summarizes connection of
these Motorola processors to the MT8885 DTMF
transceiver.
Figures 18 and 19 are the timing diagrams for the
Intel 8031/8051 (12 MHz) and 8085 (5 MHz) micro-
controllers with multiplexed address and data buses.
The MT8885 latches in the state of RD on the falling
edge of CS. When RD is high, Intel processor
operation is selected.
latch enable (ALE) output with the high-byte address
(P2) decode output, CS can be generated.
12(b) summarizes the connection of these Intel
processors to the MT8885 transceiver.
NOTE: The adaptive micro interface relies on high-
to-low
microcontroller interface and this pin must not be tied
permanently low.
MC6800/6802
low).
MC6809
A0-A15
A0-A15
D0-D3
D0-D3
transition
VMA
R/W
RW
Figure 12 a) & b) - MT8885 Interface Connections for Various Intel and Motorola Micros
Q
E
2
Additionally,
on
(a)
By NANDing the address
CS
the
to
Texas
CS
RS0
D0-D3
R/W/WR
DS/RD
CS
RS0
D0-D3
R/W/WR
DS/RD
MT8885
MT8885
recognize
Instruments
Figure
the
The adaptive micro interface provides access to five
internal registers. The read-only Receive Data
Register contains the decoded output of the last
valid DTMF digit received. Data entered into the
write-only Transmit Data Register will determine
which tone pair is to be generated (see Table 1 for
coding details). Transceiver control is accomplished
with two control registers (see Tables 6 and 7), CRA
and CRB, which have the same address. A write
operation to CRB is executed by first setting the
most significant bit (b3) in CRA. The following write
operation to the same address will then be directed
to CRB, and subsequent write cycles will be directed
back to CRA. The read-only status register indicates
the current transceiver state (see Table 8).
A software reset must be included at the beginning
of all programs to initialize the control registers upon
power-up or power reset (see Figure 14). Refer to
Tables 4-7 for bit descriptions of the two control
registers.
The multiplexed IRQ/CP pin can be programmed to
generate an interrupt upon validation of DTMF
signals or when the transmitter is ready for more
data (burst mode only). Alternatively, this pin can be
configured to provide a square-wave output of the
call progress signal. The IRQ/CP pin is an open drain
output and requires an external pull-up resistor (see
Figure 13).
MC68HC11
8031/8051
8080/8085
AD0-AD3
A8-A15
A8-A15
ALE
WR
RW
RD
DS
AS
P0
(b)
CS
D0-D3
RS0
DS/RD
R/W/WR
CS
D0-D3
RS0
DS/RD
R/W/WR
MT8885
MT8885
MT8885
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