MT9171 Mitel Networks, MT9171 Datasheet - Page 17

no-image

MT9171

Manufacturer Part Number
MT9171
Description
ISO2-CMOS ST-BUS FAMILY Digital Subscriber Interface Circuit Digital Network Interface Circuit
Manufacturer
Mitel Networks
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT9171AE
Manufacturer:
MITEL
Quantity:
5 510
Part Number:
MT9171AE
Manufacturer:
SEC
Quantity:
5 510
Part Number:
MT9171AN
Manufacturer:
MITEL
Quantity:
27
Part Number:
MT9171AN
Manufacturer:
ZARLINK
Quantity:
6 000
Part Number:
MT9171AN
Manufacturer:
ZARLINK
Quantity:
20 000
Part Number:
MT9171AN1
Manufacturer:
ZARLINK
Quantity:
230
Part Number:
MT9171ANR1
Manufacturer:
ZARLINK
Quantity:
230
Part Number:
MT9171ANR1
0
Part Number:
MT9171AP
Manufacturer:
ZARLINK
Quantity:
6 000
Part Number:
MT9171AP
Manufacturer:
ZARLINK
Quantity:
20 000
Part Number:
MT9171AP1
Manufacturer:
ZARLINK
Quantity:
1 500
Advance Information
† Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
† Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes:
AC Electrical Characteristics
AC Electrical Characteristics
6a
6b
10
11
F0b
C4
ST-BUS
BIT CELLS
1
2
3
4
5
6
1
2
3
4
5
7
8
9
Duty cycle is measured at V
C4 Clock Period
C4 Clock Width High or Low
Frame Pulse Setup Time
Frame Pulse Hold Time
Frame Pulse Width
10.24 MHz Clock Jitter (wrt C4)
O
N
P
U
S
U
P
U
S
T
T
T
I
1)
2)
Input Voltage
Input Current
Input Impedance
Crystal/Clock Frequency
Crystal/Clock Tolerance
Crystal/Clock Duty Cycle
Crystal/Clock Duty Cycle
Crystal/Clock Loading
Output Capacitance
Load Resistance
Load Capacitance
Output Voltage
When operating as a SLAVE the C4 clock has a 40% duty cycle.
When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e.,
F
0 ns to t
Characteristics
C
=2.5xf
Characteristics
C4P
Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams
C4
). The relative phase between these two clocks (
. However, the relative jitter must be less than J
DD
/2 volts.
(V
(V
Channel 31
Bias
Bias
Bit 0
, V
, V
(L
(L
(L
(L
(L
(L
(L
OUT
IN)
IN
IN
OUT
OUT
Ref
Ref
OUT
)
)
- Clock Timing - DN Mode (Figures 16 & 17)
- Voltages are with respect to ground (V
)
)
)
)
)
)
Channel 0
Sym
t
t
t
t
t
C4W
Bit 7
F0W
C4P
F0S
F0H
J
C
Sym
R
C
DC
DC
V
Z
T
C
C
I
V
f
Lout
Lout
IN
C
IN
IN
C
o
L
o
C
C
Min
-15
50
50
Channel 0
-100
Min
-10
0.1
3.2
Bit 6
20
40
45
Typ*
244
122
244
10.24
Typ*
500
100
4.3
50
50
33
0
8
C
(see Figure 17).
in Fig. 17) is not critical and may vary from
Max
+15
+100
Max
+10
5.0
4.6
40
60
55
50
20
SS
) unless otherwise stated.
Units
Units
MHz
ppm
ns
ns
ns
ns
ns
ns
V
V
k
k
µ
pF
pF
pF
µF
%
%
pp
A
pp
f
f
Normal temp. & V
Recommended at max./
min. temp. & V
From OSC1 & OSC2 to V
Capacitance to V
R
In Master Mode - Note 1
Note 2
Baud
Baud
Lout
=160 kHz
=160 kHz
= 500 , C
Test Conditions
Test Conditions
MT9171/72
DD
Lout
Bias
DD
= 20pF
.
9-149
SS
.
.

Related parts for MT9171