74LCXR162245TTR STMicroelectronics, 74LCXR162245TTR Datasheet

IC BUS TXRX 16BIT LV 48-TSSOP

74LCXR162245TTR

Manufacturer Part Number
74LCXR162245TTR
Description
IC BUS TXRX 16BIT LV 48-TSSOP
Manufacturer
STMicroelectronics
Series
74LCXRr
Datasheet

Specifications of 74LCXR162245TTR

Logic Type
Transceiver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
8
Current - Output High, Low
12mA, 12mA
Voltage - Supply
2 V ~ 3.6 V
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
497-1072-2
Order codes
Features
August 2006
5V tolerant inputs and outputs
High speed:
– t
Power down protection on inputs and outputs
Symmetrical output impedance:
– |I
PCI bus levels guaranteed 12mA
Balanced propagation delays:
– t
A and B side outputs have equivalent 26Ω
series resistors
Operating voltage range:
– V
Pin and function compatible with
74 series 16245
Latch-up performance exceeds
500mA (JESD 17)
ESD performance:
– HBM > 2000V
(MIL STD 883 method 3015); MM > 200V
PD
PLH
OH
CC
74LCXR162245TTR
= 4.2ns (Max) at V
| = I
≅ t
(Opr) = 2.0V to 3.6V
Part number
with 5V tolerant I/Os and 26Ω series resistors in the outputs
OL
PHL
= 12mA (Min) at V
Low voltage CMOS 16-bit bus transceiver (3-state)
CC
= 3V
CC
= 3V
TSSOP48
Package
Rev 4
Description
The 74LCXR162245 is a low voltage CMOS 16 bit
bus transceiver (3-state) fabricated with sub-
micron silicon gate and double-layer metal wiring
C
high speed 3.3V applications; it can be interfaced
to 5V signal environment for both inputs and
outputs.
This IC is intended for two-way asynchronous
communication between data buses; the direction
of data transmission is determined by DIR input.
The two enable inputs nG can be used to disable
the device so that the buses are effectively
isolated.
All outputs are designed to sink up to 12mA and
include a 26Ω series resistor to reduce overshoot
and undershoot.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Z State must
be held HIGH or LOW.
2
MOS technology. It is ideal for low power and
74LCXR162245
TSSOP48
Tape and reel
Packaging
www.st.com
1/15
15

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74LCXR162245TTR Summary of contents

Page 1

... Latch-up performance exceeds 500mA (JESD 17) ■ ESD performance: – HBM > 2000V (MIL STD 883 method 3015); MM > 200V Order codes Part number 74LCXR162245TTR August 2006 = Description The 74LCXR162245 is a low voltage CMOS 16 bit bus transceiver (3-state) fabricated with sub- micron silicon gate and double-layer metal wiring ...

Page 2

Contents Contents 1 Logic symbols and I/O equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin settings . . . ...

Page 3

Logic symbols and I/O equivalent circuit Figure 1. IEC logic symbols Figure 2. Input and output equivalent circuit Logic symbols and I/O equivalent circuit 3/15 ...

Page 4

Pin settings 2 Pin settings 2.1 Pin connection Figure 3. Pin connection (top through view) 4/15 74LCXR162245 ...

Page 5

Pin description Table 1. Pin description Pin N° 8,9, 11, 12 13, 14, 16, 17, 19, 20, 22 36, 35, 33, 32, 30, 29, 27, 26 47, 46, 44, 43, ...

Page 6

... STMicroelectronics sure program and other relevant quality documents. Table 3. Absolute maximum ratings ...

Page 7

Electrical characteristics Table 5. DC specifications Symbol V High level input voltage IH V Low level input voltage IL V High level output voltage OH V Low level output voltage OL I Input leakage current I Power OFF ...

Page 8

Electrical characteristics Table 7. AC electrical characteristics Symbol Parameter Propagation delay t t PLH PHL time Output enable t t PZL PZH time Output disable t t PLZ PHZ time t Output to output OSLH t skew time OSHL 1. ...

Page 9

Test circuit Figure 4. Test circuit Figure 5. Test circuit C = 50pF or equivalent (includes jig and probe capacitance) L Ω 500 or equivalent pulse generator (typically ...

Page 10

Waveforms 7 Waveforms Figure 6. Propagation delays (f = 1MHz; 50% duty cycle) Figure 7. Output enable and disable time (f = 1MHz; 50% duty cycle) 10/15 74LCXR162245 ...

Page 11

Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on ...

Page 12

Package mechanical data DIM PIN 1 IDENTIFICATION 12/15 TSSOP48 MECHANICAL DATA mm. MIN. TYP MAX. 1.2 0.05 0.15 0.9 0.17 0.27 0.09 0.20 12.4 12.6 8.1 BSC ...

Page 13

DIM Tape & Reel TSSOP48 MECHANICAL DATA mm. MIN. TYP MAX. 330 12.8 13.2 20.2 60 30.4 8.7 8.9 13.1 13.3 1.5 1.7 3.9 4.1 11.9 12.1 Package mechanical ...

Page 14

Revision history 9 Revision history Table 9. Revision history Date 15-Sep-2004 30-Aug-2006 14/15 Revision 3 Ordering Codes Revision - pag New template, temperature ranges updated 74LCXR162245 Changes ...

Page 15

... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...

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