FM25W64 Ramtron Corporation, FM25W64 Datasheet - Page 2

• Manufacturer Part Number: FM25W64
• Description: 64kb Wide Voltage Spi F-ram Features
• Manufacturer: Ramtron Corporation

Pin Description
Rev. 1.1
Dec. 2010
Pin Name
/CS
SCK
/HOLD
/WP
SI
SO
VDD
VSS
HOLD
SCK
WP
CS
Supply
Supply
Output
Input
Input
Input
Input
Input
I/O
`
Hold: The /HOLD signal is used when the host CPU must interrupt a memory operation
Pin Description
Chip Select: Enables and disables the device. When /CS is high, the output pin SO is hi-
Z, all other inputs are ignored, and the device remains in a low-power standby mode.
When /CS is low, the part will respond to the SCK signal. A falling edge on /CS must
occur for every op-code.
Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the
rising edge and outputs occur on the falling edge. The device is static so the clock
frequency may be any value between 0 and 20 MHz and may be interrupted at any time.
for another task. Asserting the /HOLD signal low pauses the current operation. The
device ignores SCK and /CS. All transitions on /HOLD must occur while SCK is low.
Write Protect: This pin prevents write operations to the status register. This is critical
since other write protection features are controlled through the status register. A
complete explanation of write protection is provided below.
Serial Input: SI is the data input pin. It is sampled on the rising edge of SCK and is
ignored otherwise. It should always be driven to a valid logic level to meet IDD
specifications.
* SI may be connected to SO for a single pin data interface.
Serial Output: SO is the data output pin. It is driven during read cycles and remains hi-Z
at all other times including when HOLD\ is low. Data transitions are driven on the falling
edge of the serial clock.
* SO can be connected to SI for a single pin data interface since the part communicates
in half-duplex.
Supply Voltage: 2.7V to 5.5V
Ground
Instruction Register
Instruction Decode
Address Register
Clock Generator
Control Logic
Write Protect
Counter
Figure 1. Block Diagram
13
Nonvolatile Status
Data I/O Register
FRAM Array
Register
1K x 64
3
8
SO
2 of 13