APL5915 Anpec Electronics Corporation, APL5915 Datasheet - Page 15

• Manufacturer Part Number: APL5915
• Description: 0.8v Reference Ultra Low Dropout 0.2v@1.5a Linear Regulator
• Manufacturer: Anpec Electronics Corporation

APL5915
Feedback Network (Cont.)
Copyright
Rev. A.3 - Apr., 2008
Application Information (Cont.)
R1(k
• Condition 3 : Low ESR (eg. Ceramic Capacitors)
C1(pF)
- The C1 calculated from equation (4) must meet
- The C1 calculated from equation (7) must meet
- Calculate the C1 as the following :
- Use equation (2) to calculate the R2.
- Calculate the R1 as the following:
- Calculate the C1 as the following :
C1(pF)
the following equation :
C1(pF)
Select a proper R1(selected) to be a little larger
than the calculated R1.
Select a proper C1(selected) to be a little smaller
than the calculated C1.
If the C1(calculated) can not meet the equation
(5), please use the Condition 3.
Select a proper R1(selected) to be a little larger
than the calculated R1. The minimum selected
R1 is equal to 1k
smaller than 1k or negative.
Select a proper C1(selected) to be a little smaller
than the calculated C1.
C1(pF)
the following equation:
Where R1=R1(selected)
Where R1=R1(calculated) from equation (3)
Where R1=R1(selected)
Where R1=R1(calculated) from equation (6)
)
(0.24
(2.1
0.033
7.2
ANPEC Electronics Corp.
ESR(m
0.71
ESR(m
1
1.25
ESR(m
ESR(m
)
R1(k
)
34.2)
143
V
300)
OUT
when the calculated R1 is
)
C
)
(V)
OUT
)
C
101
OUT
(
ESR(m
1
F)
(
C
F)
37.5
R1(k
1
OUT
R1(k
37.5
37.5
(
)
V
R1(k
F)
C
)
OUT
V
OUT
OUT
V
)
........
OUT
(V)
)
(
(V)
F)
(V)
..
..
..
(4)
..
(8)
(5)
(7)
(6)
15
The reason to have three conditions described above
is to optimize the load transient responses for all kinds
of the output capacitor. For stability only, the Condition
2, regardless of equation (5), is enough for all kinds of
output capacitor.
PCB Layout Consideration (See Figure 2)
1. Please solder the Exposed Pad and VIN together
2. Please place the input capacitors for VIN and
3. Ceramic decoupling capacitors for load must be
4. To place APL5915 and output capacitors near the
5. The negative pins of the input and output capaci-
6. Please connect PIN 3 and 4 together by a wide
7. Large current paths must have wide tracks.
8. See the Typical Application
- Connect the one pin of the R2 to the GND of
- Connect the one pin of R1 to the Pin 3 of APL5915
- Connect the one pin of C1 to the Pin 3 of APL5915
- Use equation (2) to calculate the R2.
If the C1
please use the Condition 2.
on the PCB. The main current flow is through the
load is good for performance.
tors and the GND pin of the APL5915 are con
exposed pad.
VCNTL pins near pins as close as possible.
nected to the ground plane of the load.
(See Next Page Figure 2)
placed near the load as close as possible.
APL5915
track.
(calculated)
can not meet the equation (8),
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