AN214 Philips, AN214 Datasheet - Page 11

• Manufacturer Part Number: AN214
• Description: 74F Extended Octal-Plus Family Applications
• Manufacturer: Philips

Philips Semiconductors
Metastability in Latches and Registers
Interfacing a basically asynchronous real-world with synchronous
logic systems can and does cause many circuit designer
headaches. The problem: latches and registers which are normally
considered to have only two stable states (High and Low) actually
have a third—The METASTABLE State. This third operating point
occurs when the corss-coupled latch is exactly balanced. This state
is only stable when there is no noise on the chip which would tend to
destabilize the perfect energy balance between the bi-stable states
of the latch. Refer to Figure 12.
Metastability can occur when input data violate the setup time or
hold time specifications at the clocking or strobing edge of the
synchronizing clock input. With no system noise, the latch cannot
decide “yes or no”, so it is possible for the latch to “go metastable”
or “maybe”. With noise on the chip, random energy will “nudge” the
latch toward one of its “bi-stable” states—HIGH or LOW. This
metastable state time can range from nanoseconds to milliseconds.
With today’s very high performance logic families, the metastable
condition can last for, perhaps, 1000 times the latch’s normal
propagation delay time. A metastable latch has an unpredictable
delay time during which the output is between logic levels. This
June 1988
74F extended octal-plus family applications
DATA
LE
LOW
ENERGY
G1
G2
METASTABLE POINT
ENERGY
G3
G4
Figure 12. Metastability in Latches and Registers
V
V
OG3
TH
HIGH
= 1.35V
= V
IG4
Q
Q
V
OUT
11
— OUTPUT VOLTAGE
metastable state can easily last more than 50ns with today’s high
performance logic families and WILL cause systems to “crash” if
great care is not taken with asynchronous, real-world interfacing.
The D-type latch shown in Figure 12 has DATA applied to NAND
gate 1 and DATA applied to NAND gate 2. When the LE (Latch
Enable) input is LOW, gates 1 and 2 outputs are HIGH and the G3/4
R-S latch is latched and stable. When LE is HIGH, the latch appears
to be transparent to the DATA input—Q equals DATA. On the
HIGH-to-LOW transition of LE, the DATA logic level that meets the
latch’s setup and hold time is stored in the latch.
If DATA changes during the setup time to hold time period, it is
possible for both outputs of gates 1 and 2 to be in the input
thresholds region of gates 3 and 4, respectively. Under these
conditions, the latch (gates 3 and 4) could be perfectly balanced in
the METASTABLE state. Eventually, chip and system noise will
cause the latch to be forced into a HIGH/LOW stable state.
The Extended Octal-Puls Family, while not entirely immune, has
been made metastable resistant by using design techniques which
force the latch toward a stable state much more quickly than older
bus interface families.
5.0
4.0
3.0
2.0
1.0
0
0
0.5
V
IN
— INPUT VOLTAGE
1.0
1.5
V
V
OG3
TH
2.0
= 1.35V
= V
SF01339
Application note
AN214
IG4
2.5