AN178 Philips, AN178 Datasheet - Page 13

• Manufacturer Part Number: AN178
• Description: Modeling the PLL
• Manufacturer: Philips

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Philips Semiconductors
Fortunately, it is usually sufficient to know how to improve the
lock-up time and what must be sacrificed to get faster lock-up.
Consider an operational loop or tone decoder where occasionally
the lock-up transient is too long. What can be done to improve the
situation — keeping in mind the factors that influence lock?
a. Initial phase relationship between incoming signal and VCO —
b. Low-pass filter — The larger the low-pass filter time constant, the
c. Loop damping — A simple first-order lowpass filter of the form
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Modeling the PLL
This is the greatest single factor influencing the lock time. If the
initial phase is wrong, it first drives the VCO frequency away
from the input frequency so that the VCO frequency must walk
back on the beat notes. Figure 13 gives a typical distribution of
lock-up times with the input pulse initiated at random phase. The
only way to overcome this variation is to send phase information
all the time so that a favorable phase relationship is guaranteed
at t = 0. For example, a number of PLLs or tone decoders may
be weakly locked to low amplitude harmonics of a pulse train and
the transmitted tone phase related to the same pulse train.
Usually, however, the incoming phase cannot be controlled.
longer will be the lock-up time. The lock-up time can be reduced
by decreasing the filter time constant, but in doing so, some of
the noise immunity and out-band signal rejection will be
sacrificed. This is unfortunate, since this is what necessitated
the use of a large filter in the first place. Also present will be a
sum frequency (twice the VCO frequency) component at the low
pass filter and greater phase jitter resulting from out-band signals
and noise. In the case of the tone decoder (where control of the
capture range is required since it specifies the device bandwidth)
a lower value of low-pass capacitor automatically increases the
bandwidth. Speed is gained only at the expense of added
bandwidth.
Damping can be increased not only by reducing , as discussed
above, but also by reducing the loop gain K
produces a loop damping of
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Figure 13. Probability of Lock vs Input Cycles
F(s)
1 2
1
1
1
K
s
V
V
. Using the loop
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(67)
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d. Input frequency deviation from free-running frequency —
e. In-band input amplitude — Since input amplitude is one factor in
f. Out-band signals and noise — Low levels of extraneous signals
g. Center frequency — Since lock-up time can be described in
However, because of the wide variation due to initial phase, the
reverse may be true for any single trial.
PLL MEASUREMENT TECHNIQUES
This section deals with measurements of PLL operation. The
techniques suggested are meant to help the designer in evaluating
the performance of the PLL during the initial setup period as well as
to point out some pitfalls that may obscure loop evaluation.
Recognizing that the test equipment may be limited, techniques are
described which require a minimum of standard test items.
The majority of the PLL tests described can be done with a signal
generator, a scope and a frequency counter. Most laboratories have
these. A low cost digital voltmeter will facilitate accurate
measurement of the VCO conversion gain. Where the need for a
FM generator arises, it may be met in most cases by the VCO of a
Philips Semiconductors PLL. Any of the loops may be set up to
operate as a VCO by simply applying the modulating voltage to the
low-pass filter terminal(s). The resulting generator may be checked
for linearity by using the counter to check frequency as a function of
modulating voltage. Since the VCOs may be modulated right down
to DC, the calibration may be done in steps. Moreover, loop
measurements may be made by applying a constant frequency to
the loop input and the modulating signal to the low-pass filter
terminal to simulate the effect of a FM input so that an FM generator
may be omitted for many measurements.
gain reduction to control bandwidth or capture and lock ranges
achieves better damping for narrow bandwidth operation. The
penalty for this damping is that more phase comparator output is
required for a given deviation so that phase errors are greater
and noise immunity is reduced. Also, more input drive may be
required for a given deviation.
Naturally, the further an applied input signal is from the
free-running frequency of the loop, the longer it will take the loop
to reach that frequency due to the charging time of the low-pass
filter capacitor. Usually, however, the effect of this frequency
deviation is small compared to the variation resulting from the
initial phase uncertainty. Where loop damping is very low,
however, it may be predominant.
the phase comparator’s gain K
loop gain K
the input amplitude is low, the lock-up time may be limited by the
rate at which the low-pass capacitor can charge with the reduced
phase comparator output (see d above).
and noise have little effect on the lock-up time, neither improving
or degrading it. However, large levels may overdrive the loop
input stage so that limiting occurs, at which point the in-band
signal starts to be suppressed. The lower effective input level
can cause the lock-up time to increase, as discussed in e above.
terms of the number of cycles to lock, fastest lock-up is achieved
at higher frequencies. Thus, whenever a system can be
operated at a higher frequency, lock will typically take place
faster. Also, in systems where different frequencies are being
detected, the higher frequencies, on the average, will be
detected before the lower frequencies.
v
damping is also a function of input amplitude. When
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d
, and since K
d
is a factor in the
Application note
AN178