PIC17C42 Microchip Technology, PIC17C42 Datasheet - Page 92

• Manufacturer Part Number: PIC17C42
• Description: High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
• Manufacturer: Microchip Technology

PIC17C4X
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
6.
FIGURE 13-8: ASYNCHRONOUS RECEPTION
TABLE 13-6:
DS30412C-page 92
Address
16h, Bank 1
13h, Bank 0
14h, Bank 0
17h, Bank 1
15h, Bank 0
17h, Bank 0
Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', shaded cells are not used for asynchronous reception.
Note 1: Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
(RA4/RX/DT pin)
baud rate.
the SYNC bit and setting the SPEN bit.
pletes and an interrupt will be generated if the
RCIE bit was set.
Initialize the SPBRG register for the appropriate
Enable the asynchronous serial port by clearing
If interrupts are desired, then set the RCIE bit.
If 9-bit reception is desired, then set the RX9 bit.
Enable the reception by setting the CREN bit.
The RCIF bit will be set when reception com-
Rcv buffer reg
(interrupt flag)
Read Rcv
buffer reg
OERR bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
Rcv shift
RCREG
reg
CREN
RCIF
Name
PIR
RCSTA
RCREG
PIE
TXSTA
SPBRG
RX
causing the OERR (overrun) bit to be set.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
bit
Baud rate generator register
CSRC
SPEN
RBIF
RBIE
Bit 7
RX7
bit0
TMR3IF TMR2IF TMR1IF
TMR3IE TMR2IE TMR1IE
bit1
Bit 6
RX9
RX6
TX9
SREN
TXEN
Bit 5
RX5
bit7/8
CREN
SYNC
Bit 4
RX4
Stop
bit
Word 1
RCREG
Start
CA2IF
CA2IE
bit
Bit 3
RX3
—
—
bit0
7.
8.
9.
CA1IF
FERR
CA1IE
Note:
Bit 2
RX2
—
Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred dur-
ing reception.
Read RCREG for the 8-bit received data.
If an overrun error occurred, clear the error by
clearing the OERR bit.
bit7/8
OERR
TRMT
To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
Bit 1
TXIF
TXIE
RX1
Stop
bit
Word 2
RCREG
RX9D
TX9D
RCIF
RCIE
Bit 0
RX0
Start
bit
1996 Microchip Technology Inc.
0000 0010
0000 -00x
xxxx xxxx
0000 0000
0000 --1x
xxxx xxxx
Power-on
Value on
Reset
bit7/8
Stop
Word 3
bit
other resets
Value on all
0000 0010
0000 -00u
uuuu uuuu
0000 0000
0000 --1u
uuuu uuuu
(Note1)