PIC17C42 Microchip Technology, PIC17C42 Datasheet - Page 73

• Manufacturer Part Number: PIC17C42
• Description: High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
• Manufacturer: Microchip Technology

12.1
12.1.1
Both Timer1 and Timer2 will operate in 8-bit mode
when the T16 bit is clear. These two timers can be inde-
pendently configured to increment from the internal
instruction cycle clock or from an external clock source
on the RB4/TCLK12 pin. The timer clock source is con-
figured by the TMRxCS bit (x = 1 for Timer1 or = 2 for
Timer2). When TMRxCS is clear, the clock source is
internal and increments once every instruction cycle
(Fosc/4). When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the timer will increment on every
falling edge of the RB4/TCLK12 pin.
The timer increments from 00h until it equals the Period
register (PRx). It then resets to 00h at the next incre-
ment cycle. The timer interrupt flag is set when the timer
is reset. TMR1 and TMR2 have individual interrupt flag
bits. The TMR1 interrupt flag bit is latched into TMR1IF,
and the TMR2 interrupt flag bit is latched into TMR2IF.
Each timer also has a corresponding interrupt enable
bit (TMRxIE). The timer interrupt can be enabled by set-
ting this bit and disabled by clearing this bit. For periph-
eral interrupts to be enabled, the Peripheral Interrupt
Enable bit must be enabled (PEIE is set) and global
interrupts must be enabled (GLINTD is cleared).
The timers can be turned on and off under software
control. When the Timerx On control bit (TMRxON) is
set, the timer increments from the clock source. When
TMRxON is cleared, the timer is turned off and cannot
cause the timer interrupt flag to be set.
FIGURE 12-3: TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE
1996 Microchip Technology Inc.
Timer1 and Timer2
TIMER1, TIMER2 IN 8-BIT MODE
RB4/TCLK12
Fosc/4
Fosc/4
TMR1CS
(TCON1<0>)
TMR2CS
(TCON1<1>)
1
0
0
1
TMR1ON
(TCON2<0>)
TMR2ON
(TCON2<1>)
Comparator<8>
Comparator<8>
Comparator x8
Comparator x8
12.1.1.1
When TMRxCS is set, the clock source is the
RB4/TCLK12 pin, and the timer will increment on every
falling edge on the RB4/TCLK12 pin. The TCLK12 input
is synchronized with internal phase clocks. This causes
a delay from the time a falling edge appears on TCLK12
to the time TMR1 or TMR2 is actually incremented. For
the external clock input timing requirements, see the
Electrical Specification section.
TMR1
TMR2
PR1
PR2
EXTERNAL CLOCK INPUT FOR TIMER1
OR TIMER2
Equal
Equal
Reset
Reset
Set TMR1IF
(PIR<4>)
Set TMR2IF
(PIR<5>)
PIC17C4X
DS30412C-page 73