PIC16C926-I/CL Microchip Technology, PIC16C926-I/CL Datasheet - Page 52

• Manufacturer Part Number: PIC16C926-I/CL
• Description: 64/68-Pin CMOS Microcontrollers with LCD Driver
• Manufacturer: Microchip Technology

PIC16C925/926
6.4
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 6-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 6-1:
TABLE 6-2:
DS39544A-page 50
Note 1: Higher capacitance increases the stability
0Bh, 8Bh,
10Bh, 18Bh
0Ch
8Ch
0Eh
0Fh
10h
Legend:
32.768 kHz
Osc Type
Address
100 kHz
200 kHz
These values are for design guidance only.
LP
2: Since each resonator/crystal has its own
Timer1 Oscillator
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by theTimer1 module.
of the oscillator but also increases the
start-up time.
characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components.
INTCON
PIR1
PIE1
TMR1L
TMR1H
T1CON
Name
Epson C-001R32.768K-A
Epson C-2 100.00 KC-P
100 kHz
200 kHz
32 kHz
STD XTL 200.000 kHz
Freq
CAPACITOR SELECTION FOR
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
THE TIMER1 OSCILLATOR
Crystals Tested:
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
LCDIF
LCDIE
Bit 7
GIE
—
33 pF
15 pF
15 pF
PEIE
ADIF
ADIE
Bit 6
C1
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
TMR0IE
Bit 5
—
—
33 pF
15 pF
15 pF
20 PPM
20 PPM
20 PPM
C2
Preliminary
INTE
Bit 4
—
—
SSPIF
SSPIE
RBIE
Bit 3
6.5
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1.
Timer1 must be configured for either Timer or Synchro-
nized Counter mode, to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take pre-
cedence.
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively become the period register for
Timer1.
6.6
TMR1H and TMR1L registers are not reset on a POR
or any other RESET, except by the CCP1 special event
trigger.
T1CON register is reset to 00h on a Power-on Reset.
In any other RESET, the register is unaffected.
6.7
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Note:
TMR0IF
CCP1IF
CCP1IE
Bit 2
Resetting Timer1 Using the CCP
Trigger Output
Resetting of Timer1 Register Pair
(TMR1H:TMR1L)
Timer1 Prescaler
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TMR2IE
TMR2IF
Bit 1
INTF
2001 Microchip Technology Inc.
TMR1IE 00-- 0000 00-- 0000
TMR1IF
RBIF
Bit 0
0000 000x 0000 000u
00-- 0000 00-- 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Power-on
Value on
Reset
Value on
RESETS
all other