ISL1209 Intersil Corporation, ISL1209 Datasheet - Page 16

• Manufacturer Part Number: ISL1209
• Manufacturer: Intersil Corporation

DIGITAL TRIMMING REGISTER (DTR <2:0>)
The digital trimming bits DTR0, DTR1, and DTR2 adjust the
average number of counts per second and average the ppm
error to achieve better accuracy.
• DTR2 is a sign bit. DTR2 = “0” means frequency
• DTR1 and DTR0 are both scale bits. DTR1 gives 40ppm
A range from -60ppm to +60ppm can be represented by
using these three bits (see Table 13).
Alarm Registers
Addresses [0Ch to 11h]
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode:
• Single Event Mode is enabled by setting the ALME bit to
• Interrupt Mode is enabled by setting the ALME bit to “1”,
compensation is >0. DTR2 = “1” means frequency
compensation is <0.
adjustment and DTR0 gives 20ppm adjustment.
“1”, the IM bit to “0”, and disabling the frequency output.
This mode permits a one-time match between the alarm
registers and the RTC registers. Once this match occurs,
the ALM bit is set to “1” and the IRQ output will be pulled
low and will remain low until the ALM bit is reset. This can
be done manually or by using the auto-reset feature.
the IM bit to “1”, and disabling the frequency output. The
DTR2
0
0
0
0
1
1
1
1
TABLE 13. DIGITAL TRIMMING REGISTERS
DTR REGISTER
DTR1
0
0
1
1
0
0
1
1
16
DTR0
0
1
0
1
0
1
0
1
FREQUENCY
ESTIMATED
0 (default)
PPM
+20
+40
+60
-20
-40
-60
0
ISL1209
To clear an alarm, the ALM bit in the status register must be
set to “0” with a write. Note that if the ARST bit is set to 1
(address 07h, bit 7), the ALM bit will automatically be cleared
when the status register is read.
Below are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1 – Alarm set with single interrupt (IM=”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm registers as follows:
B. Also the ALME bit must be set as follows:
xx indicate other control bits
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the ALM bit in the
status register to “1” and also bringing the IRQ output low.
Example 2 – Pulsed interrupt once per minute (IM=”1”)
Interrupts at one minute intervals when the seconds register
is at 30 seconds.
A. Set Alarm registers as follows:
B. Set the Interrupt register as follows:
xx indicate other control bits
REGISTER
REGISTER
CONTROL
ALARM
IRQ output will now be pulsed each time an alarm occurs.
This means that once the interrupt mode alarm is set, it
will continue to alarm for each occurring match of the
alarm and present time. This mode is convenient for
hourly or daily hardware interrupts in microcontroller
applications such as security cameras or utility meter
reading.
MNA
MOA
DWA
SCA
HRA
DTA
INT
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0 HEX
0 1 x
x 0 0 0 0
BIT
BIT
00h Seconds disabled
B0h Minutes set to 30,
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
x0h Enable Alarm
enabled
enabled
enabled
enabled
disabled
DESCRIPTION
DESCRIPTION
February 1, 2005
FN6109.0