ISL1209 Intersil Corporation, ISL1209 Datasheet - Page 14

• Manufacturer Part Number: ISL1209
• Manufacturer: Intersil Corporation

ARST is cleared to “0”, the user must manually reset the
BAT and ALM bits.
INTERRUPT CONTROL REGISTER (INT)
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the IRQ/F
Table 8 for frequency selection. When the frequency mode is
enabled, it will override the alarm mode at the IRQ/F
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the F
backup mode (i.e. V
FOBATB is set to “1” the F
battery backup mode. This means that both the frequency
output and alarm output functions are disabled. When the
FOBATB is cleared to “0”, the F
during battery backup mode.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
V
V
08h
Default
FREQUENCY,
ADDR
BAT
DD
32768
F
< V
4096
1024
1/16
1/32
supply will be used when V
1/2
1/4
1/8
OUT
TABLE 7. INTERRUPT CONTROL REGISTER (INT)
64
32
16
TABLE 8. FREQUENCY SELECTION OF F
0
8
4
2
1
TRIP
IM ALME LPMODE FOBATB FO3 FO2 FO1 FO0
7
0
. With LPMODE = “1”, the device will be in low
6
0
UNITS
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
BAT
5
0
power source active). When the
FO3
OUT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
14
OUT
/IRQ pin is disabled during
OUT
DD
4
0
/IRQ pin during battery
/IRQ pin is enabled
FO2
< V
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
OUT
BAT
3
0
- V
pin. See
FO1
OUT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
2
0
BATHYS
PIN
OUT
1
0
FO0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
and
pin.
0
0
ISL1209
power mode and the V
V
about 600nA when using LPMODE = “1” with V
(See Typical Performance Curves: I
LPMODE ON & OFF.)
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
interrupt alarm (see IM bit).
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/F
triggered by the alarm as defined by the alarm registers (0Ch
to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/F
tied low until the ALM status bit is cleared to “0”.
EVENT DETECTION REGISTER (EV)
The ISL1209 provides an easy to use event and tamper
detection circuit. The Event Detection Register configures
the functionality of the event detection circuits.
EVENT INPUT SAMPLING SELECTION BITS
(ESMP<1:0>)
These two bits select the rate of sampling of the EVIN pin to
trigger an event detection. For example, a 2Hz sampling rate
would configure the ISL1209 to check the status of the EV
pin twice a second. Slower sampling significantly reduces
the supply current drain.
NOTE: In order to use the sampling mode time-based hysteresis
must be activated. See Table 11.
DD
ESMP1
< V
IM BIT
0
0
1
1
0
1
BAT
- V
BATHYS
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By Alarm
ESMP0
BAT
INTERRUPT/ALARM FREQUENCY
0
1
0
1
. There is a supply current saving of
TABLE 10.
TABLE 9.
supply will be used when
OUT
EVENT SAMPLING RATE
DD
pin when the RTC is
vs VDD with
Always ON
OUT
1
2Hz
1Hz
/
4
Hz
DD
pin will be
February 1, 2005
= 5V.
FN6109.0