SDA9362 Infineon Technologies Corporation, SDA9362 Datasheet
SDA9362
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SDA9362 Summary of contents
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ICs for Consumer Electronics DDC-PLUS-Deflection Controller SDA 9362 Data Sheet 1998-02-01 ...
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Edition 1998-02-01 This edition was realized using the software system FrameMaker Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third ...
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SDA 9362 Revision History: Previous Version: Page Page (in previous (in current Version) Version Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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DDC-PLUS-Deflection Controller 1 Overview 1.1 Features • Deflection - Protection - 16:9 / 4:3 2 • C Bus alignment of all deflection parameters • All EW-, V- and H-functions (incl. • PW EHT compensation • PH EHT compensation • Compensation ...
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General Description The SDA 9362 is a highly integrated deflection controller for CTV receivers with doubled line and standard or doubled field frequencies. It controls among others an horizontal driver circuit for a flyback line output stage ...
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Pin Description Pin No. Symbol Type 1 CLL I/TTL SDA IQ 5 SCL I 6 HSYNC I/TTL 7 VBLE Q/TTL 8 SCP DD( SS(D) 11 ...
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Pin Description (cont’d) Pin No. Symbol Type 27 SW1 Q/TTL 28 VSYNC I/TTL TEST I/TTL 31 TST0 I 32 TST1 I 33 HDEDEF I/TTL 34 SSD I/TTL 35 TST4 I 36 TST5 O 37 TST6 ...
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Block Diagram SCL 2 C SDA RESN HDEDEF TST0 TEST Control TST1 VSYNC HSYNC CLL CLKI PLL Figure 2 Semiconductor Group SCP SCAN HPROT SSD VPROT Protection Start REFC REFL REFH ...
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System Description 2.1 Functional Description The main input signals are HSYNC with doubled horizontal frequency, VSYNC with vertical frequencies of 50/100 Hz or 60/120 Hz and the line locked clock CLL. The output signals control the horizontal as well ...
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VPROT: Vertical sawtooth voltage V < first half of V-period > second half: HD disabled i The pin SCP delivers the composite blanking signal SCP. It contains burst ( blanking HBL ( V ...
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Circuit Description The system clock for the SDA 9362 has to be generated externally (e.g. in the SDA 9206) and applied to pin CLL. Its frequency must be always the line frequency (defined by the horizontal time reference HSYNC) ...
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Reset Modes The circuit is only completely reset at power-on/off (timing diagram refer 5.3). If the pin RESN has L-level or during standby operation some parts of the circuit are not affected (timing diagram refer 5.4): Power-On-Reset HD output ...
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If NSA = 0 (subaddress 01 and 680 for each specified H-frequency. 2 2.5 C-Bus Control I 2 2.5.1 I C-Bus Address 2.5.2 I C-Bus Format write ...
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I C-Bus Commands Control Item Allowed Deflection control Deflection control Vertical shift -128..127 -128..127 H ...
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The effective range for Vertical Blanking Time: 16 ... 127 (absolute value) 0 ... 127 (offset value) b) The "default value if disabled" for Vertical Blanking Time: 21 (absolute value) 8 (offset value) c) The effective range for Start ...
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SW2: Setting of output SW2 0: output SW2 has L-level 1: output SW2 has H-level BD: Blanking disable 0: horizontal and vertical blanking enabled 1: horizontal and vertical blanking disabled SW1: Setting of output SW1 0: output SW1 has L-level ...
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NSA: No self adaptation 0: self adaptation on 1: self adaptation off STE: Scan time enable 0: control items for vertical scan width 0 and width 1 are disabled 1: control items for vertical scan width 0 and width 1 ...
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NI: Non interlace 0: interlace depends on source 1: no interlace The Internal Voltage Ref Control Byte includes the following bits: BANDG5 BANDG4 BANDG3 BANDG2 BANDG1 BANDG0 BANDG BANDG5 ... Adjustment of internal bandgap reference BANDG0:100000: Reference Output voltage min ...
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PONRES: Power On Reset 0: after bus master has read the status byte 1: after each detected reset Note: PONRES is reset after this byte has been read. 2.5.5 Explanation of Some Control Items Start Vertical Scan If enabled (SSE ...
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It defines the start of the reduced amplitude (factors 0.5, 0.66, 0.75) of the vertical sawtooth (refer page 35). When Start Reduced Scan = 0 the reduction takes place over all lines including vertical flyback. b) control bits VR1, ...
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Additional to the control items Vertical angle, Vertical bow and Horizontal shift, this product influences the horizontal phase at the output HD according to the following equation: AFC EHT compensation = --------------------------------------------------------------- - * V * IBEAM variation of horizontal ...
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HSYNC VSYNC Start of odd Field VD- VBL (BSE = 0) VBL (BSE = 1, VBT = 16) 2 Lines VBL (BSE = 1, VBT = 25) 3 Lines VBL (BSE = 1, VBT = 26) Figure 4 Vertical Blanking ...
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Case of STE = 1 In this case the control item Vertical blanking time is an extension for the V-blanking pulse BSE = 1 and VBT = 0 the V-blanking pulse has its minimum: it starts always ...
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HSYNC VSYNC VD- 4 Lines VBL (BSE = 0) VBL (BSE = 1, VBT = 0) 3 Lines VBL (BSE = 1, VBT = 7) Figure 5 Vertical blanking pulse VBL when STE = 1 Semiconductor Group ...
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Minimum Number of Lines per Field It defines the minimum number of lines per field for the vertical synchronisation. If the TV standard at the inputs VSYNC and HSYNC has less lines per field than defined by Minimum Number of ...
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Most Important V-Deflection Modes for 4:3 CRT Description Characteristics N0 Normal mode Self adaptation (for 4:3 source, scan start = line 9 Letterbox) start of V-ramp = line 9 with default scan time: depends on source signal settings guard band ...
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Most Important V-Deflection Modes for 16:9 CRT Description Characteristics N0 Normal mode Self adaptation (for 16:9 or scan start = line 9 4:3 source) with start of V-ramp = line 9 default settings scan time: depends on source signal guard ...
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Absolute Maximum Ratings Parameter Operating temperature Storage temperature Junction temperature Soldering temperature Input voltage Output voltage Supply voltages Supply total voltage differentials Total power dissipation Latch-up protection 1) Between any internally non-connected supply pin of the same kind. All ...
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Recommended Operating Conditions Parameter Symbol Supply voltages V Ambient temperature T TTL Inputs: CLL, HSYNC, VSYNC, TEST, SSD, HDEDEF, RESN H-input voltage V L-input voltage V Input VPROT Threshold V1 Threshold V2 Input HPROT Threshold V1 Threshold V2 Input ...
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Recommended Operating Conditions (cont’d) Parameter Symbol Input VSYNC Pulse width high Pulse width high Input capacitance C Input CLL Input frequency f I Input capacitance C Quartz Oscillator Input / Output X1, X2 Crystal frequency Crystal resonant impedance External ...
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Characteristics (Assuming Recommended Operating Conditions) Parameter Symbol Average supply I CC current Standby supply current Output Pins: VBLE, SW1, SW2 Output low level V Output high level V Input / Output SDA Output low level V Output SCP Output ...
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Characteristics (Assuming Recommended Operating Conditions) (cont’d) Parameter Symbol DAC Output VD+, VD- DAC resolution DAC output low (VD-) DAC output high (VD-) DAC output low (VD-) - (VD+) DAC output high (VD-) - (VD+) Load capacitance C Output load ...
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Application Information 2 TV Contr. C NVM 24.576 MHz VSYNC Source Sel HSYNC Synch Sep LF Figure 6 Semiconductor Group HD SDA 9362 E/W VD- VD+ VPROT 34 SDA 9362 V EHT B ...
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Waveforms 5.1 VD- Output Voltage, 4/3-CRT and 16/9-Source V VD- V 0(max) V 0(min) 2 SRS 0 SRSE = 1 Start Reduced Scan (SRS) selectable (line 0, 2...63) Figure 7 Semiconductor Group ...
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Function of H,V Protection HPROT ... Depends on ...
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Power On/Off Diagram Supply Voltage Power- On- Reset 32 Cycles X1, X2 SSD = 0: ~ 250 SSD = 1: ~ 380 Bus Tristate V , REFP V , REFH V REFL Active Protection Inactive 2 ...
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Standby Mode, RESN Diagram Standby RESN HD 2-Loop Active CPU Inactive Active V , REFP V , Inactive REFH V REFL Active Protection Inactive 2 C Bus 2 C Reg. Programmable 01 ... ...
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Package Outlines P-MQFP-44-2 (Plastic Metric Quad Flat Package) 0.8 0.3 +0. Index Marking 1) Does not include plastic or metal protrusions of 0.25 max per side Figure 10 Sorts of Packing Package outlines for tubes, trays ...