SDA9290-6 Infineon Technologies Corporation, SDA9290-6 Datasheet - Page 5

• Manufacturer Part Number: SDA9290-6
• Description: Picture Processor
• Manufacturer: Infineon Technologies Corporation

I
An I
and modes of the picture processor. Via this interface up to four registers can be written according
to the following transfer protocol for controlling the operation mode:
S: Start condition
A: Acknowledge
P: Stop condition
Slave address: 0 0 1 0 1 0 1
(Note: There is a general description of the I
After every data byte that is transmitted the internal register address (subaddress) is automatically
incremented to the next register so that, if necessary, several registers can be loaded with one I
Bus telegram.
In the multi-picture mode the operating mode transmitted on the I
vertical blanking interval, i.e. during the high phase of signal VS1, if the Memory Sync Controller
(MSC) activates the DREQ line during this period.
It should be noted that the new operating mode has always to be transmitted to the picture
processor first and immediately afterwards to the MSC on the I
30 ms.
This is the only way to ensure interference-free synchronization of the picture processor and the
MSC. The four I
right-hand margin are set by an internally generated reset signal (default values) when the
operating voltage is applied.
Register Sub-
R0
R1
R2
R3
Semiconductor Group
S
2
C Bus Interface
2
Slave Address
C Bus interface configured as a “slave receiver” is used for programming the different functions
Description”.)
address
00
01
02
03
2
C Bus registers are described below in more detail. The values marked “*D” in the
1)
D7
B1
YF5
LINE2
SNTEN SNT1
0 A
D6
B0
YF4
LINE1
Sub Address
D5
FR
YF3
LINE0
SNT0
2
C Bus in the Siemens publication “I
5
A
D4
0
SL4
SU4
KTEN
Data Byte
Data Byte
D3
SS
SL3
SU3
KT3
2
C Bus at an interval not longer than
2
C Bus is switched within the
D2
VCR
SL2
SU2
KT2
A
D1
NR
SL1
SU1
KT1
2
C Bus Technical
SDA 9290-6
1997-07-22
D0
SUV8
SL0
SU0
KT0
A P
2
C