SDA9290-6 Infineon Technologies Corporation, SDA9290-6 Datasheet - Page 2

• Manufacturer Part Number: SDA9290-6
• Description: Picture Processor
• Manufacturer: Infineon Technologies Corporation

The necessary decimation and interpolation operations are activated automatically
when the format is set. Together with a corresponding Memory Sync Controller
(SDA 9220) it enables functions like multi-picture, tuner scanning, picture-in-still and
still-in-picture. The different modes can be activated by a microcontroller on the I
interface (slave receiver). The I
Circuit Description
The core of the picture processor (see block diagram) is formed of the Image-lmproving
Processor (IIP) and the Multi-Picture Processor (MPP). The IIP is responsible for noise
and cross-color reduction, while the MPP together with the new Memory Sync Controller
implements the functions multi-picture, tuner scanning, picture-in-still and still-in-picture.
Image-lmproving Processor
The signal inputs Yl0-YI7 and UVI0-UVI7 and the back-channel signal inputs YB0-YB7
and UVB0-UVB7 picture data with 12 bits in quasi-parallel format (4:1:1) and with 16 bits
in parallel format (4:2:2). The clock rate for both signals is 13.5 MHz. For signal
processing in the IIP and MPP the chrominance bit levels have to be separated in the
case of the quasi parallel format by demultiplexers DEMUXS and DEMUXR, these being
largely identical in design.
A reduction in video noise is achieved by correlating the picture contents of two
successive fields, the non-correlated components (noise) being attenuated by the digital
filter. To achieve this, the instantaneous digital picture signal on the outputs of the
demultiplexer DEMUXS and the picture signal delayed by a field interval on the outputs
of the back-channel demultiplexer DEMUXR are fed to the IIP and combined.
The signal-to-noise ratio (
the movement detector uses this information to select an appropriate set of parameters
with filter coefficients and thresholds for the comparators. For this purpose the
luminance signal is assigned to one of three classes according to its
class defining a different degree of maximum noise reduction. The limits between the
middle class and the upper and lower classes can be programmed by the I
registers R1 and R2 with the values for the thresholds SU and SL. When the picture
signals come from a video cassette recorder, the adaptation on the
signal should be disabled by I
Measurement of the signal-to-noise ratio in the automatic mode has been advanced
from line 6 to line 4 in order to avoid conflicts with future text and data services.
The degree of noise reduction for the luminance and chrominance signals can be varied
between 0 dB and 12 dB by selecting the appropriate filter coefficients.
Semiconductor Group
0
0
1
S/N
0
) unit detects the noise components of the input signals and
2
L-Bus register R0, VCR bit D2.
2
C-Bus address for accessing the device is
1
2
0
1
0
S/N
S/N
ratio of the input
ratio, with each
SDA 9290-6
1997-07-22
2
2
C-Bus
C-Bus