SDA9257 Infineon Technologies Corporation, SDA9257 Datasheet - Page 20

• Manufacturer Part Number: SDA9257
• Description: Clock SYNC Generator
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
2.2.1 Output Coding for Straight Binary / Two’s Complement Mode
Straight binary or Two’s complement output coding is selectable for each separate signal
component (Y and UV) via
For straight binary coding a special suppression of code 0 and code 255 is provided in
output format mode according CCIR 656.
Table 1
Output Coding
Step
Underflow
0
1
2
•
•
253
254
255
Overflow
V
resp. AINU, AINV
Table 1 is valid for
CY
,
V
CU, V
: ext. clamping level during clamping at
AINY
<
>
V
V
V
V
•
•
V
V
V
V
CY
CY
CY
CY
CY
CY
CY
CY
- 0.125 V
- 0.125 V
- 0.117 V
- 0.109 V
+ 1.859 V
+ 1.867 V
+ 1.875 V
+ 1.875 V
V
REFL
= 2.2 V and
I
2
C-Bus control bits YCODE and UVCODE.
AINU, AINV
<
>
•
•
V
V
V
V
V
V
V
V
CU, V
CU, V
CU, V
CU, V
CU, V
CU, V
CU, V
CU, V
+ 0.992 V
+ 0.984 V
- 1.0 V
- 0.992 V
- 0.984 V
+ 1.0 V
+ 1.0 V
- 1.0 V
V
REFH
20
= 4.2 V, xAMP = 0000
Bit
0
0
0
0
•
•
0
0
0
1
OFL
C
ext cl
UFL
Bit
1
0
0
0
•
•
0
0
0
0
on channel AINY
Straight
Binary
7 65 4 3 21 0
0 0 00 0 0 00
0 0 00 0 0 00
0 0 00 0 0 01
0 0 00 0 0 10
•
•
1 1 11 1 1 01
1 1 11 1 1 10
1 1 11 1 1 11
1 1 11 1 1 11
Two’s
Complement
7 65 4 3 2 1 0
1 0 00 0 0 0 0
1 0 00 0 0 0 0
1 0 00 0 0 0 1
1 0 00 0 0 1 0
•
•
0 1 11 1 1 0 1
0 1 11 1 1 1 0
0 1 11 1 1 1 1
0 1 11 1 1 1 1
SDA 9206
1999-02-10