SDA9257 Infineon Technologies Corporation, SDA9257 Datasheet - Page 16

• Manufacturer Part Number: SDA9257
• Description: Clock SYNC Generator
• Manufacturer: Infineon Technologies Corporation

Semiconductor Group
2.1.3 Clamping
The analog pins AINY, AINU, AINV are switched simultaneously to on chip generated
clamping levels by an on chip clamping pulse H2.
Analog Channel
AINY
AINU, AINV
The external clamping capacitance is loaded by on chip current sources during
clamping. So loading time depends on the values of
2.1.4 Digital Decimation Filters for YUV
The data rates of digital YUV signals are reduced in decimation filters following the
A/D conversion. The overall performance of the decimation filters is tuned to the
requirements for TV signals.
In figure 11 the frequency response of the filter for the Y channel is shown. The input
sampling rate is 27 MHz, the output sampling rate is 13.5 MHz.
Figure 11
Magnitude Frequency Response of the Luminance Filter
The Input Sampling Frequency
-10
-20
-30
-40
-50
dB
10
0
0
Straight Binary
Code
0001 0000
1000 0000
0.1
f
S
is 27 MHz
0.2
16
Two’s Complement
Code
1001 0000
0000 0000
0.3
C
ext cl
.
0.4
f /
Y
U, V
Components
f
S
UED10459
0.5
SDA 9206
1999-02-10