SDA9254-2 Infineon Technologies Corporation, SDA9254-2 Datasheet - Page 31

• Manufacturer Part Number: SDA9254-2
• Description: 2.6mb Dynamic Sequential Access Memory For Television Applications (tv-sam) With On-chip Noise Reduction Filter
• Manufacturer: Infineon Technologies Corporation

Application Information
Digital Storage of a TV Field
As standard for digital TV systems, CCIR recommendation 601 defines a field of 288 lines with
720 pixels per line. The sampling frequency is 13.5 MHz with a resolution of 8 bit per pixel.
Information is stored in 3 different channels: one channel for luminance (Y), two channels for
chrominance (U and V).
The bandwidth ratio between the different channels is either Y:U:V = 4:1:1 or 4:2:2 depending on
the coding method.
The bus width for the 4:1:1 format is 12 bit, the 4:2:2 format requires 16 bit and a SDA 9251-2X
memory device additionally.
The SDA 9254-2 is designed for low cost large area flicker- and noise reduction systems. The
following block diagram shows a typical application for 4:1:1 signals.
Figure 9
Low Cost Flicker- and Noise Reduction System with SDA 9254-2
Semiconductor Group
YIN
UIN
VIN
CVBS
Triple ADC
SDA 9206
CSG
+
SYNC
12
SDA 9254-2
SDA 9220-5
MSC
31
Address
12
SYNC
Processor
SDA 9280
Display
YOUT
UOUT
VOUT
To Deflection
UEB08607
SDA 9254-2
1998-01-16