SDA9254-2 Infineon Technologies Corporation, SDA9254-2 Datasheet
SDA9254-2
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SDA9254-2 Summary of contents
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MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter Preliminary Data Features Stores a complete video field (4:1:1) On chip adaptive recursive noise reduction filter (4:1:1) 4 noise reduction classes selectable Special noise reduction ...
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Functional Description General The SDA 9254 combination of the TV-SAM SDA 9253 and an adaptive recursive filter to achieve a reduction of noise for video signals. To get a closed loop one of the two output ports of ...
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CLASS Figure 2 Noise Reduction with 4:2:2 Signals Adaptive Field Based Noise Reduction The reduction of noise is performed by recursive filtering. The filter has the following transfer function: For ...
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SDC0 ... 11 DEMUX Video Input 12 Input 8 Luminance Motion CLASS Detector 3 delayed Luminance 8 Memory DEMUX Port B 12 Figure 3 Block Diagram of the Noise Reduction Filtering To avoid artefacts in moving parts of the picture ...
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The following diagram shows the requested data format for 4:1:1 signals at the input SDC0 … SDC11. The output data format at pins SQA0 … SQA11 corresponds to the input format. BLN 13.5 MHz SDC 4 ... 11 Y1 SDC ...
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Circuit Description Memory Architecture As shown in the block diagram of the memory part (see figure 7), the TV-SAM comprises 192 memory arrays, which are accessed in parallel. Each memory array has a size of 212 rows by 64 columns. ...
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Write Transfer from Latch C to Memory (RE) The data of latch C are transferred to the preaddressed location of the memory array at the rising edge of RE, if the mode bits were set to H (M1) and L ...
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Data Output A (SQA, SCA, OEA) Data is shifted out through the serial port A (SQA0 … SQA11) at the rising edge of the shift clock SCA. After 16 clock cycles new data have to be transferred from latch A ...
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The beginning of a block of 16 serial data at port determined by RA and RB, respectively. The end of the serial input data block at port C is controlled by WT. Since RA, RB and ...
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Figure 5 Typical Memory Cycle Sequence Semiconductor Group 10 SDA 9254-2 1998-01-16 ...
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Pin Configuration (top view) SDC4 SDC5 SCA SAR SAC SCAD RE V DD1 V SS1 CLASS2 SCB SDC6 SDC7 Figure 6 Semiconductor Group P-MQFP-64 ...
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Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) 15 SQA11 SQA8 . 21 SQA7 . 22 SQA6 . 27 SQA5 . 28 SQA4 O 31 SQA3 ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 61 CLASS2 I 12 DLO3 O 11 DLO2 O 10 DLO1 O 9 DLO0 O 37 DLI3 I 38 DLI2 I 39 DLI1 I 40 DLI0 I 43 ...
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Port B OEB SCB 12 Shift Port C Register C Latch 212 Figure 7 Block Diagram of the Memory Semiconductor Group DD1 ...
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Absolute Maximum Ratings Parameter Storage temperature Soldering temperature Soldering time Input/output voltage Power supply voltage Data out current (short circuit) Total power dissipation Power dissipation per output Operating Range Parameter Supply voltage Supply voltage Supply voltage Supply voltage H-input voltage ...
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DC Characteristics Parameter Symbol H-output voltage L-output voltage QL Input leakage I I (L) current I Output leakage Q (L) current Average supply ...
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AC Characteristics Parameter Symbol Memory read write cycle time t RE low time RE t Serial port cycle SC time t RE precharge ...
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AC Characteristics (cont’ Parameter Symbol lead time t WRL lead time t RWL t Output buffer turn- OFF off delay ...
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AC Characteristics (cont’ Parameter Symbol Refresh period t REF t Transition time T (rise/fall) L-serial clock time t SCL t H-serial clock time SCH Hold time ...
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Operation Truth Table RE Cycle N SCAD SAR SAC M0 RA0…RA CA0… RA0…RA CA0… RA0…RA CA0… ...
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Input conditions : Output conditions Output loading: Diagram 1 AC-Timing Measuring Conditions Semiconductor Group 2 0 ...
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RE t ROH t ROS SCAD SAR RA6 RA7 RA0 SAC L L CA0 RA t RRL OEA SCA SQA(0-11) Diagram 2 Read Transfer Memory to Port A Semiconductor Group ...
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RE t ROS SCAD t SAR RA6 RA7 RA0 SAC H L CA0 RB t RRL SCB Port B Diagram 3 Read Transfer Memory to Port B Semiconductor Group ROH ...
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RE t ROS SCAD t AS SAR RA6 RA7 RA0 SAC L H CA0 WT SCB t DS Port Diagram 4 Write Transfer from Port C to Memory Semiconductor Group ROH t ...
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Serial Read Operation Port SCA t CAA OEA t OAA SQA(0-11) Serial Read Operation Port SCB t CBA OEB t OBA Port B Serial Write Operation Port SCB Port C Diagram ...
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RE t ROS SCAD SAC H H Diagram 6a Refresh with Internal Row Address Semiconductor Group ROH SDA 9254 UED08620 1998-01-16 ...
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RE t ROS SCAD t AS SAR RA6 RA7 RA0 * ) * ) SAC LLH LHL * ) Mode bits arbitrary, except combination M0 = "H" and M1 = "H" Mode bits should toggle in successive cycles ...
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SCB BLN DLN OEDLO DLO t ODA Diagram 7 Timing of BLN, DLI and DLO Semiconductor Group CBH t CBA 28 SDA 9254 UET08618 1998-01-16 ...
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SC SCB SDC B1 Port B Port C t RSS Delay t RSH RB t RPW WT Diagram 8 RB, WT Timing Restrictions Semiconductor Group B10 C1 C2 ...
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Application Circuit For best performance and operation within the specified AC parameter limits it is mandatory to use separate decoupling capacitors for V shorted to on the board as shown in figure below. DD2 C Decoupling capacitors and 1 To ...
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Application Information Digital Storage Field As standard for digital TV systems, CCIR recommendation 601 defines a field of 288 lines with 720 pixels per line. The sampling frequency is 13.5 MHz with a resolution of 8 bit ...
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Package Outlines P-MQFP-64-1 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 32 SDA 9254-2 Dimensions in mm 1998-01-16 ...