DS3514 Maxim Integrated Products, DS3514 Datasheet - Page 11

• Manufacturer Part Number: DS3514
• Manufacturer: Maxim Integrated Products

The DS3514 operates in one of three modes that deter-
mine how the V
controlled/updated. The first two modes allow “banked”
control of the 14 gamma channels and one V
nel. Depending on the mode, one of four banks (in
EEPROM) can be selected using either the S0/S1 pins
or using the SOFT S0/S1 bits in the Soft S0/S1 register.
Once a bank is selected, the LD pin can then be used
to simultaneously update each channel’s DAC output.
The third and final mode is not banked. It allows I
control of each channel’s Latch A register that is SRAM
(volatile), allowing quick and unlimited updates. In this
mode, the LD pin can also be used to simultaneously
update each channel’s DAC output. A detailed descrip-
tion of the three modes as well as additional features of
the DS3514 follows.
The DS3514 mode of operation is determined by two
bits located in Control register (CR, register 48h), which
is nonvolatile (NV) (EEPROM). In particular, the mode is
determined by the MODE0 bit (CR.0) and the MODE1
bit (CR.1). Table 1 illustrates how the two control bits
are used to select the operating mode. When shipped
from the factory, the DS3514 is programmed with both
MODE bits set to zero.
As shown in the Block Diagram , each channel contains
four words of EEPROM that are used to implement the
“banking” functionality. Each bank contains unique
DAC settings for each channel. When the DS3514 is
configured in this operating mode, the desired bank is
selected using the S0 and S1 pins as shown in Table 2
where 0 is ground and 1 is V
S1 are both connected to ground, the first bank (Bank
A) is selected. Once a bank is selected, the timing of
the DAC update depends on the state of LD pin. When
LD is high, Latch B functions as a flow-through latch, so
the amplifier responds asynchronously to changes in
Table 1. Operating Modes
S0/S1 Pin-Controlled Bank-Updating Mode
MODE1 BIT
(CR.1)
0
0
1
I
2
MODE0 BIT
C Gamma and V
______________________________________________________________________________________
(CR.0)
COM
0
1
X
Detailed Description
and gamma DACs are
CC
S0/S1 Pin-Controlled Bank
Updating (Factory Default)
S0/S1 Bit-Controlled Bank
Updating
I
Control
2
C Individual Channel
. For example, if S0 and
Mode Selection
MODE
COM
chan-
2
C
COM
the state of S0/S1 to meet the t
Conversely, when LD is low, Latch B functions as a
latch, holding its previous data. A low-to-high transition
on LD allows the Latch B input data to flow through and
update the DACs with the EEPROM bank selected by
S0/S1. A high-to-low transition on LD latches the select-
ed DAC data into Latch B.
This mode also features banked operation with the only
difference being how the desired bank is selected. In
particular, the bank is selected using the SOFT S0 (bit
0) and SOFT S1 (bit 1) bits contained in the Soft S0/S1
register (40h). The S0 and S1 pins are ignored in this
mode. Table 2 illustrates the relationship between the
bit settings and the selected bank. For example, if
SOFT S0 and SOFT S1 are written to zero, the first bank
(Bank A) is selected. Once a bank is selected, the tim-
ing of the DAC update depends on the state of the LD
pin. When LD is high, Latch B functions as a flow-
through latch, so the amplifier responds asynchronous-
ly to changes in the state of the SOFT S0/S1 bits. These
are changed by an I
low, Latch B functions as a latch, holding its previous
data. A low-to-high transition on LD allows the Latch B
input data to flow through and update the DACs with
the EEPROM bank selected by the SOFT S0/S1 bits. A
high-to-low transition on LD latches the selected DAC
data into Latch B.
Because the Soft S0/S1 register is SRAM, subsequent
power ups result in the SOFT S0 and SOFT S1 bits
being cleared to 0 and, hence, powering up to Bank A.
In this mode the I
channel Latch A registers to update a single DAC (i.e.,
not banked). The Latch A registers are SRAM and not
EEPROM. This allows an unlimited number of write
cycles as well as quicker write times since t
applies to EEPROM writes. As shown in the Memory
Table 2. Bank Selection Table
SOFT S0/S1 Bit-Controlled Bank-Updating
S1
BIT OR PIN
0
0
1
1
Buffer with EEPROM
I
2
C Individual Channel-Control Mode
S0
0
1
0
1
2
C master writes directly to individual
V
V
V
V
2
COM
COM
COM
COM
CHANNEL
C write. Conversely, when LD is
V
COM
Bank A
Bank B
Bank C
Bank D
SEL
GM1–GM14 Bank A
GM1–GM14 Bank B
GM1–GM14 Bank C
GM1–GM14 Bank D
CHANNELS
specification.
GAMMA
W
Mode
only
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