R1610C RDC Semiconductor, R1610C Datasheet - Page 15
R1610C
Manufacturer Part Number
R1610C
Description
High Performance 16 Bits MCU Integrated One 10/100M Mac Controller - 3.3V Operating Voltage/2.5V Core Voltage
Manufacturer
RDC Semiconductor
Datasheet
1.R1610C.pdf
(145 pages)
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R
● JTAG /SCAN Chain Enable Pin
● SDRAM Interface
● GPIO Interface
Data Sheet
Final Version 1.5
October 27, 2003
R
PIN No.
PIN No.
PIN No.
104
118
103
102
119
74
85
84
82
86
64
39
41
42
D
32
33
D
C
C
®
®
PIO29/UARTX0
R
R
I
I
PHY_CHG1
S
S
C
C
SD_CLK
JTAGEN
Symbol
Symbol
Symbol
D
D
RXER1
CAS_n
RAS_n
MDIO1
DQMH
DQML
PIO27
PIO28
MDC1
WE_n
S
S
COL1
P
P
NC
C
C
o
o
m
m
m
m
u
u
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
I/O/PU* General purpose PIN.
I/O/PU* General purpose PIN.
I/O/PD*
I/O/PD
I/O/PD
I/O/PD
Type
Type
Type
I/PD
I/PD
O
O
O
O
O
O
O
end of the packet.
Receiver error shall be asserted to indicate to MAC that an error
was detected. This signal should be synchronized with the RXC
signal.
This pin functions as the collision detection. When the external
physical layer protocol (PHY) device detects a collision, it
asserts this pin.
MII management data clock is sourced by the R1610C to the
external PHY devices as a timing reference for the information
transfer on the MDIO signal.
MII management data input/output transfers control information
and status between the external PHY and the R1610C.
To indicate PHY status changed.
JTAG function enable. Default is pulled low and disabled.
Not connected
SDRAM clock ouput. This clock output is from internal De-skew
PLL. It can be one to four multiple of input clock X1, depending
on the setting of PDIVD [2:0] during power-on resets.
SDRAM write enable.
SDRAM column address selector.
SDRAM raw address selector.
Input/Output mask.
Input/Output mask.
General purpose PIN.
UARTX0: URAT0 transmission indication for observation.
Fast Ethernet RISC Processor
Description
Description
Description
R1610C
15
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