PIC16C72-02/SS Microchip Technology, PIC16C72-02/SS Datasheet - Page 31
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PIC16C72-02/SS
Manufacturer Part Number
PIC16C72-02/SS
Description
8-Bit CMOS Microcontrollers with A/D Converter
Manufacturer
Microchip Technology
Datasheet
1.PIC16C72-02SS.pdf
(124 pages)
- Current page: 31 of 124
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6.0
The Timer2 module timer has the following features:
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (Both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to gen-
Timer2 has a control register, shown in Figure 6-2.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Figure 6-1 is a simplified block diagram of the Timer2
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Reference Manual,
DS33023.
6.1
Timer2 can be used as the PWM time-base for PWM
mode of the CCP module.
The TMR2 register is readable and writable, and is
cleared on any device reset.
The input clock (F
1:4
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
TMR2 is not cleared when T2CON is written.
1998 Microchip Technology Inc.
erate clock shift
Watchdog Timer reset, or Brown-out Reset)
or
TIMER2 MODULE
Timer2 Operation
1:16,
OSC
selected
/4) has a prescale option of 1:1,
by
control
Preliminary
bits
6.2
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
6.3
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
FIGURE 6-1:
Note 1: TMR2 register output can be software selected
Sets flag
bit TMR2IF
Postscaler
1:1
Timer2 Interrupt
Output of TMR2
to
by the SSP Module as a baud clock.
PIC16C72 Series
1:16
4
TMR2
output
Reset
EQ
TIMER2 BLOCK DIAGRAM
(1)
Comparator
TMR2 reg
PR2 reg
1:1, 1:4, 1:16
Prescaler
DS39016A-page 31
2
F
OSC
/4
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