TSS901E ATMEL Corporation, TSS901E Datasheet
TSS901E
Related parts for TSS901E
TSS901E Summary of contents
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... The TSS901E may also be used in single board systems where standardised high speed interfaces are needed and systems containing "non-intelligent" modules such as A/D-converter or sensor interfaces which can be assembled with the TSS901E thanks to the " ...
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... Std 1355-1995 specification carrying the simple interprocessor communication proto- (1) col and a data processing node consisting of a CPU and communication and data memory. The TSS901E provides HW supported execution of the major parts of the sim- ple interprocessor communication protocol, particularly: • transfer of data between two modes of a multi-processor system with minimal host CPU intervention, • ...
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... Additionally the HOCI contains the interrupt signalling capability of the TSS901E by providing an interrupt output, the interrupt status register and interrupt mask register to the local CPU. A special pin is provided to select between control of the TSS901E by HOCI or by link. If control by link is enabled, the host data bus functions as a 32-bit general pur- pose interface (GPIO). ...
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... Operation Modes Rev. C – 24-Aug-01 According to the different protocol formats expected for the operation of the TSS901E, two major operation modes are implemented into the TSS901E. The operation modes are chosen individually for each link channel by setting the respective configuration reg- isters via the HOCI or via the link. ...
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... A feature of the TSS901E is the possibility to control the TSS901E not only via HOCI but via one of the three links. This allows to use the TSS901E in systems without a local controller (µController, FPGA etc.). Since the HOCI is no longer used in this operation mode instead available as a set of general purpose I/O (GPIO) lines. ...
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... The IEEE Std 1355-1995 specifies low level checks as link disconnect detection and parity check at token level. The TSS901E provides, through the Protocol Processing Unit, features to reset a link or all links inside the TSS901E, to reset the local CPU or to send special signals to the CPU commanded via the links. ...
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... HDATA0 - HDATA7 The registers of the TSS901E are Bytes wide. That means, if the HOCI data port bit mode, 4 read or write accesses are necessary to access a 4 Byte register (e. g. the interrupt mask register). In 16/32 bit mode the data bits are ' bit register is read. Rev. C – ...
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... Rev. C – 24-Aug-01 The addresses of the TSS901E registers are directly mapped with pins HADR7 - 0. The tables below shows the addresses of all the TSS901E registers depending on the HOCI port width. Register SICR TSS901E Interface Control Register TRS_CTRL Transmit-Speed-Base Register ...
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... TSS901E channel 2 status and control registers Port Width / Address (hex TSS901E 9 Register CH1_CNTRL1 channel 1 control Register 1 CH1_CNTRL2 ...
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... TSS901E channel 3 status and control registers Port Width / Address (hex Rev. C – 24-Aug-01 Register CH2_PR_STAR channel 2 Protocol Status Register CH2_CNTRL1 channel 2 control Register 1 CH2_CNTRL2 ...
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... TSS901E 11 Register CH3_DSM_TSTR channel 3 DSM test Register CH3_ADDR channel 3 address Register CH3_RT_ADDR channel 3 Route address Register CH3__PR_STAR channel 3 Protocol Status Register CH3_CNTRL1 channel 3 control Register 1 CH3_CNTRL2 channel 3 control Register 2 CH3_HTID channel 3 Header Transaction ID byte ...
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... Rev. C – 24-Aug-01 These registers are only enabled when the TSS901E is configured for "control by link" using the ’BOOTLINK’ pin. Register GPIO_DIR0 GPIO direction register 0 GPIO_DIR1 GPIO direction register 1 GPIO_DIR2 GPIO direction register 2 GPIO_DIR3 GPIO direction register 3 ...
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... The Figure below shows the TSS901E (also called SMCS332) embedded in a typical module environment: This section describes the pins of the TSS901E. Groups of pins represent busses where the highest number is the MSB Output Input High Impedance; (*) = active low signalO using a config- uration with two TSS901Es these signals can directly be connected together (WIROR) ...
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... Communication memory write strobe. This pin is asserted O/Z when the TSS901E writes to data memory. Communication memory address. The TSS901E outputs an O/Z address on these pins. Communication memory data. The TSS901E inputs and IOZ outputs data from and to com. memory on these pins. I Communication interface ’occupied’ input signal O/Z Communication interface ’ ...
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... Test Data Output. Serial scan output of the boundary scan t CKH O/Z path. TSS901E Reset. Sets the TSS901E to a known state. This input must be asserted (low) at power-up. The minimum width I of RESET low is 5 cycles of CLK10 in parallel with CLK running. External clock input to TSS901E (max. 25 Mhz). ...
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... 2 Although specified for TTL outputs, all TSS901E outputs are CMOS compatible and will drive to VCC and GND assuming no dc loads. Max. power consumption figures (at 5.5V, 125°C) are: Operation Mode not clocked TSS901E in RESET TSS901E in IDLE Maximum Symbol ...
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... PLL Filter TSS901E 17 The pin PLLOUT should be connected as shown below 249 ± 5%, ¼1/ 1nF, ± 5%, 200V C2 = 15nF, ± 5%, 200V TSS90E PLLOUT Rev. C – 24-Aug-01 ...
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... CLK period CLK width high CLK width low 1) CLK10 period CLK10 width high CLK10 width low Rev. C – 24-Aug-01 Description 1) Note: Max. 25 MHz Description 1) Note: Typically 10 MHz TSS901E Symbol Min. Max CLK t 17 CLKH t 17 CLKL Symbol Min. Max. t 100 ...
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... Reset RESET setup before CLK high RESET low pulse width Output disable after CLK high Output enable after CLK high CAM, HOSTBIGE, BOOTLINK setup before RESET high TSS901E 19 Description Symbol Min. Max RSTS RSTW CLK t 42 OUTD OUTE ...
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... HDATA valid before HACK high HDATA hold after HRD*, HSEL* inactive or TSS901EADR invalid Rev. C – 24-Aug-01 Description 1) Note: 1) Signal HACK active when HRD* low and HSEL* low and TSS901EADR = TSS901EID 2) Signal HACK disable when HRD* high or HSEL* high or TSS901EADR ¼ TSS901EID Symbol Min ...
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... Host Write HSEL*, HWR* and TSS901EADR and HADR setup before CLK high HADR, TSS901EADR hold after HSEL*, HWR* high HWR* pulse width high HACK low after HWR*, HSEL* active and TSS901EADR valid HACK high after HSEL* and HWR* and TSS901EADR = TSS901EID ...
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... CMADR CMDATA hold after CMCS0* or CMCS1* or CMRD* high or new address on CMADR Rev. C – 24-Aug-01 t CRCA CLK CMCS0 CMCS1 t CRCA CMRD CMWR t CRCA CMADR CMDATA Description TSS901E t CRCH t CRPW t CRCH t CRPW t t CRPW CRCA Addr. Valid Addr. Valid Addr. Valid t t CRDS ...
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... CMCS0*, CMCS1* and CMWR* low and CMADR valid after CLK high CMCS0*, CMCS1* or CMWR* high after CLK high CMCS0*, CMCS1*, CMWR* pulse width CMDATA valid after CLK high CMDATA valid before CMCS0* or CMCS1* or CMWR* high CMDATA hold after CMCS0* or CMCS1* or CMWR* high TSS901E 23 t CLK CWCA CMCS0 ...
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... COM Interface disable after CLK low COM Interface enable after CLK high COCI setup before CLK low COCO low after CLK low COCO high after CLK high 3) COCO pulse width Rev. C – 24-Aug-01 Description 3) Note content of COMI_ACR TSS901E Symbol Min. Max CAID t 22 CAIE t 2 ...
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... CPUR, SES, Interrupt CPUR*, SESx*, HINTR* delay after CLK high Links Bit Period LDOx, LSOx output skew Data/Strobe edge separation TSS901E 25 CLK CPUR SESx HINTR Description LSOx LDOx t LOUT LDIx t LDSI LSIx Description t OUTC Symbol Min. Max OUTC t LBITP t LOUT ...
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... TMS, TDI setup before TCK high TMS, TDI hold after TCK high TDO delay after TCK low TRST* pulse width TSS901E Inputs setup before TCK high TSS901E Inputs hold after TCK high TSS901E Outputs delay after TCK low Rev. C – 24-Aug-01 TCK TMS TDI TDO ...
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... Mechanical Data Package Dimensions TSS901E 27 MQFPL 196 Code: FX Date:13/10/00 Rev. C – 24-Aug-01 ...
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... GND 22 HADR0 23 HADR1 24 HADR2 25 HADR3 26 HADR4 27 HADR5 28 HADR6 29 HADR7 30 VCC 31 GND 32 BOOTLINK 33 TSS901EADR0 34 TSS901EADR1 35 TSS901EADR2 36 TSS901EADR3 37 TSS901EID0 38 TSS901EID1 39 TSS901EID2 40 TSS901EID3 41 VCC 42 GND 43 HDATA0 44 HDATA1 Rev. C – 24-Aug-01 Name Pin Number 67 HDATA18 68 HDATA19 69 HDATA20 70 HDATA21 71 HDATA22 72 HDATA23 73 VCC 74 GND 75 HDATA24 76 HDATA25 77 HDATA26 ...
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... HDATA8 54 HDATA9 55 HDATA10 56 HDATA11 57 VCC 58 GND 59 HDATA12 60 HDATA13 61 HDATA14 62 HDATA15 63 HDATA16 64 HDATA17 65 VCC 66 GND TSS901E 29 Name Pin Number 111 CMADR8 112 CMADR9 113 CMADR10 114 CMADR11 115 VCC 116 GND 117 CMADR12 118 CMADR13 119 CMADR14 120 CMADR15 121 CMDATA0 122 ...
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... Ordering Information Part-number TSS901EMA-E TSS901EAM 5962-01A1701QXC TSS901EA/883(*) TSS901EASC 5962-01A1701VXC TSS901EASB TSS901EAS/883(*) TSS901EMC-E 5962-01A1701Q9A 5962-01A1701V9A Rev. C – 24-Aug-01 Temp. Range 25°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C -55°C +125°C 25° ...
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... Atmel Nantes SA, 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...