TS68020 ATMEL Corporation, TS68020 Datasheet - Page 23

• Manufacturer Part Number: TS68020
• Description: Hcmos 32-bit Virtual Memory Mpu, 16/20/25 MHZ
• Manufacturer: ATMEL Corporation

Functional
Description
Description of Registers
2115A–HIREL–07/02
Figure 18. Data Capacitance Derating Curve
As shown in the programming models (Figure 19 and Figure 20) the TS68020 has six-
teen 32-bit general-purpose registers, a 32-bit program counter, two 32-bit supervisor
stack pointers, a 16-bit status register, a 32-bit vector base register, two 3-bit alternate
function code registers, and two 32-bit cache handling (address and control) registers.
Registers D0-D7 are used as data registers for bit and bit field (1- to 32-bit), byte (8-bit),
long word (32-bit), and quad word (64-bit) operations. Registers A0-A6 and the user,
interrupt, and master stack pointers are address registers that may be used as software
stack pointers or base address registers. In addition, the address registers may be used
for word and long word operations. All of the 16 (D0-D7, A0-A7) registers may be used
as index registers.
The status register (Figure 21) contains the interrupt priority mask (three bits) as well as
the condition codes: extend (X), negated (N), zero (Z), overflow (V), and carry (C). Addi-
tional control bits indicate that the processor is in the trace mode (T1 or T0),
supervisor/user state (S), and master/interrupt state (M).
All microprocessors of the TS68000 Family support instruction tracing (via the T0 status
bit in the TS68020) where each instruction executed is followed by a trap to a user-
defined trace routine. The TS68020 adds the capability to trace only the change of flow
instructions (branch, jump, subroutine call and return, etc.) using the T1 status bit.
These features are important for software program development and debug.
The vector base register is used to determine the runtime location of the exception vec-
tor table in memory, hence it supports multiple vector tables so each process or task can
properly manage exceptions independent of each other.
TS68020
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