PIC14000-04 Microchip Technology, PIC14000-04 Datasheet - Page 49

• Manufacturer Part Number: PIC14000-04
• Description: 28-Pin Programmable Mixed Signal Controller
• Manufacturer: Microchip Technology

7.5.1
In slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISC<7:6> or TRISD<1:0> are
set). The I
the output data when required (slave-transmitter).
When an address is matched or the data transfer from
an address match is received, the hardware
automatically will generate the acknowledge (ACK)
pulse, and then load the I
value in the I
There are two conditions that will cause the I
not to give this ACK pulse. These are if either (or both)
occur:
• the Buffer Full (BF), I
• the Overflow (I
TABLE 7-2:
Status Bits as Data Transfer
1996 Microchip Technology Inc.
before the transfer was received, or
before the transfer was received.
BF
0
1
1
0
SLAVE MODE
is Received
2
C module will override the input state with
2
CSR.
2
COV), I
DATA TRANSFER RECEIVED BYTE ACTIONS
I
2
COV
2
0
0
1
1
CSTAT<0>, bit was set
2
CCON<6> bit was set
2
CBUF with the received
I
2
CSR-> I
Yes
2
No
No
No
C module
2
CBUF
Preliminary
Generate ACK Pulse
In this case, the I
I
happens when a data transfer byte is received, given
the status of the BF and I
show the conditions where user software did not
properly clear the overflow condition. The BF flag is
cleared by reading the I
I
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I
module is shown in the AC timing specifications.
2
2
2
CBUF, but the I
COV bit is cleared through software.
C specification as well as the requirement of the I
Yes
No
No
No
2
CIF bit is set. Table 7-2 shows what
2
CSR value is not loaded into the
2
COV bits. The shaded boxes
(I
2
CBUF register while the
2
C interrupt if enabled)
PIC14000
Set I
DS40122B-page 49
2
Yes
Yes
Yes
Yes
CIF bit
2
C