PIC12CE67 Microchip Technology, PIC12CE67 Datasheet - Page 57

• Manufacturer Part Number: PIC12CE67
• Description: 8-Pin/ 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory
• Manufacturer: Microchip Technology

9.7
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
example, by execution of a SLEEP instruction. During
normal operation, a WDT time-out generates a device
RESET (Watchdog Timer Reset). If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled
(Section 9.1).
9.7.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
FIGURE 9-16: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 9-17: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
2007h
81h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
Note: PSA and PS2:PS0 are bits in the OPTION register.
1998 Microchip Technology Inc.
DD
Watchdog Timer (WDT)
WDT PERIOD
and process variations from part to part (see
by
clearing
Name
Config. bits
OPTION
WDT Timer
Enable Bit
WDT
configuration
(1)
From TMR0 Clock Source
(Figure 7-5)
MCLRE
GPPU
Bit 7
bit
0
1
INTEDG
WDTE
PSA
Bit 6
CP1
M
U
X
Preliminary
T0CS
Bit 5
CP0
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out early and generating a premature
device RESET condition.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.7.2
It should also be taken into account that under worst
case conditions (V
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
0
Note:
PWRTE
Time-out
8 - to - 1 MUX
MUX
T0SE
Bit 4
WDT
Postscaler
WDT PROGRAMMING CONSIDERATIONS
When the prescaler is assigned to the
WDT, always execute a CLRWDT instruction
before changing the prescale value, other-
wise a WDT reset may occur.
1
8
WDTE
Bit 3
PSA
DD
PSA
To TMR0 (Figure 7-5)
PIC12CE67X
= Min., Temperature = Max., and
FOSC2
Bit 2
PS2
PS2:PS0
FOSC1
Bit 1
PS1
DS40181B-page 57
FOSC0
Bit 0
PS0