PIC12CE67 Microchip Technology, PIC12CE67 Datasheet - Page 56

• Manufacturer Part Number: PIC12CE67
• Description: 8-Pin/ 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory
• Manufacturer: Microchip Technology

PIC12CE67X
9.5.1
An overflow (FFh
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 7.0)
9.5.2
External interrupt on GP2/INT pin is edge triggered:
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 9.8 for details on SLEEP mode.
9.5.3
An input change on GP3, GP1 or GP0 sets flag bit
GPIF (INTCON<0>). The interrupt can be enabled/dis-
abled
(INTCON<3>). (Section 5.1)
EXAMPLE 9-1:
DS40181B-page 56
MOVWF
SWAPF
BCF
MOVWF
:
:(ISR)
:
SWAPF
MOVWF
SWAPF
SWAPF
by
TMR0 INTERRUPT
INT INTERRUPT
GPIO INTCON CHANGE
on
setting/clearing
the
W_TEMP
STATUS,W
STATUS,RP0
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
SAVING STATUS AND W REGISTERS IN RAM
00h) in the TMR0 register will set
GP2/INT
pin,
enable
flag
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Change to bank zero, regardless of current bank
;Save status to bank zero STATUS_TEMP register
;Swap STATUS_TEMP register into W
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
;(sets bank to original state)
bit
bit
GPIE
INTF
Preliminary
9.6
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt i.e., W register and STATUS
register. This will have to be implemented in software.
The example:
a)
b)
c)
d)
e)
Example 9-1 store and restore the STATUS and W
registers. The register, W_TEMP, must be defined in
both banks and must be defined at the same offset
from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1).
Stores the W register.
Stores the STATUS register in bank 0.
Executes the ISR code.
Restores the STATUS register (and bank select
bit).
Restores the W register.
Context Saving During Interrupts
1998 Microchip Technology Inc.