MPC9608 Motorola Inc, MPC9608 Datasheet - Page 6

• Manufacturer Part Number: MPC9608
• Description: 1:10 LVCMOS Zero Delay Clock Buffer
• Manufacturer: Motorola Inc

www.DataSheet4U.com
MPC9608
Power Supply Filtering
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the V
tics, for instance I/O jitter. The MPC9608 provides separate
power supplies for the output buffers (V
phase-locked loop (V
sign technique is to isolate the high switching noise digital out-
puts from the relatively sensitive internal analog phase-locked
loop. In a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of isolation
may be required. The simple but effective form of isolation is a
power supply filter on the V
illustrates a typical power supply filter scheme. The MPC9608
frequency and phase stability is most susceptible to noise with
spectral content in the 100 kHz to 20 MHz range. Therefore the
filter should be designed to target this range. The key parame-
ter that needs to be met in the final filter design is the DC volt-
age drop across the series filter resistor R
sheet the I
pin) is typically 4 mA (8 mA maximum), assuming that a mini-
mum of 3.125 V must be maintained on the V
sistor R
have a resistance of 9
drop criteria.
defined by the required filter characteristics: the RC filter should
provide an attenuation greater than 40 dB for noise whose
spectral content is above 100 kHz. In the example RC filter
shown in Figure 3 “V
frequency is around 3-5 kHz and the noise attenuation at
100 kHz is better than 42 dB.
of an individual capacitor, its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low imped-
ance path to ground exists for frequencies well above the band-
width of the PLL. Although the MPC9608 has several design
features to minimize the susceptibility to power supply noise
6
V
CC
The MPC9608 is a mixed analog/digital product. Its analog
R
The minimum values for R
As the noise frequency crosses the series resonant point
CCA
F
= 9-10
F
shown in Figure 3 “V
(PLL) power supply impacts the device characteris-
CCA
Figure 3. V
current (the current sourced through the V
for V
CC
R
CCA
CCA
F
–
= 3.3 V
33...100 nF
C
CCA
10
) of the device. The purpose of this de-
F
Power Supply Filter”, the filter cut-off
CCA
Power Supply Filter
(V
F
CCA
CC
10 nF
pin for the MPC9608. Figure 3
and the filter capacitor C
C
= 3.3 V) to meet the voltage
Power Supply Filter” must
F
= 1 F for V
Freescale Semiconductor, Inc.
For More Information On This Product,
F
V
MPC9608
. From the data
CCA
V
CCA
CC
CC
CC
APPLICATIONS INFORMATION
) and the
pin. The re-
= 3.3 V
Go to: www.freescale.com
F
CCA
are
(isolated power and grounds and fully differential PLL), there
still may be applications in which overall performance is being
degraded due to system power supply noise. The power supply
filter schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most designs.
Using the MPC9608 in Zero-delay Applications
MPC9608. Designs using the MPC9608, as LVCMOS PLL
fanout buffer with zero insertion delay, will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9608 clock driver allows for its use as a zero delay buffer.
By using the QFB output as a feedback to the PLL the
propagation delay through the device is virtually eliminated.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting in a near zero delay through the
device. The maximum insertion delay of the device in
zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of the
static phase offset, I/O jitter (phase or long-term jitter), feedback
path delay and the output-to-output skew error relative to the
feedback output.
Calculation of Part-to-Part Skew
where critical clock signal timing can be maintained across sev-
eral devices. If the reference clock inputs of two or more
MPC9608 are connected together, the maximum overall timing
uncertainty from the common CCLK input to any output is:
nents: static phase offset, output skew, feedback board trace
delay, and I/O (phase) jitter:
CCLK
QFB
Any Q
Any Q
Max. skew
QFB
Figure 4. MPC9608 maximum device-to-device skew
Nested clock trees are typical applications for the
The MPC9608 zero delay buffer supports applications
t
This maximum timing uncertainty consists of 4 compo-
SK(PP)
Device 1
Common
Device 1
Device2
Device 2
= t
( )
+ t
t
SK(O)
JIT( )
-t
( )
+t
+ t
SK(O)
PD, LINE(FB)
+t
( )
t
JIT( )
t
SK(PP)
+ t
JIT( )
TIMING SOLUTIONS
t
+t
PD,LINE(FB)
SK(O)
CF