MPC9456 Freescale Semiconductor, MPC9456 Datasheet - Page 7

• Manufacturer Part Number: MPC9456
• Description: 2.5V AND 3.3V LVCMOS CLOCK FANOUT BUFFER
• Manufacturer: Freescale Semiconductor

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Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091. In
most high performance clock networks point-to-point
distribution of signals is the method of choice.
point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
thus only a single terminated line can be driven by each
output of the MPC9456 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 3. “Single
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9456 clock driver is effectively doubled due to its
capability to drive multiple lines.
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9456 output buffer is more than
sufficient to drive 50
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9456. The output waveform in Figure 4. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36
TIMING SOLUTIONS
IN
IN
The MPC9456 clock driver was designed to drive high
This technique draws a fairly high level of DC current and
The waveform plots in Figure 4. “Single versus Dual Line
Figure 3. Single versus Dual Transmission Lines
resistance to V CC 2.
MPC9456
MPC9456
OUTPUT
OUTPUT
BUFFER
BUFFER
14
14
R S = 36
R S = 36
R S = 36
transmission lines on the incident
series resistor plus the output
Freescale Semiconductor, Inc.
Z O = 50
Z O = 50
Z O = 50
For More Information On This Product,
APPLICATIONS INFORMATION
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OutA
OutB0
OutB1
In a
the
7
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 5. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
At the load end the voltage will double, due to the near
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 5. Optimized Dual Line Termination
Figure 4. Single versus Dual Waveforms
MPC9456
OUTPUT
BUFFER
14
t D = 3.8956
2
In
OutA
14 + 22
V L = V S ( Z 0
Z 0 = 50 || 50
R S = 36 || 36
R 0 = 14
V L = 3.0 ( 25
= 1.31V
4
R S = 22
R S = 22
25 = 25
k
6
22 = 50
TIME (nS)
t D = 3.9386
(R S +R 0 +Z 0 ))
(18+14+25)
OutB
8
Z O = 50
Z O = 50
k
10
50
MPC9456
12
MOTOROLA
14