MT8924AS Zarlink Semiconductor, MT8924AS Datasheet

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MT8924AS

Manufacturer Part Number
MT8924AS
Description
MT8924 - PCM Conference Circuit (PCC)
Manufacturer
Zarlink Semiconductor
Datasheet

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Features
Applications
DSTi
Supports up to 10 independent conferences for
up to 32 PCM Voice Channels
ST-BUS compatible 2.048 Mb/s PCM Serial
Interface (also supports 1.536 Mb/s and 1.544
Mb/s data rates)
Per channel digital gain control (0/-3/-6 dB)
Parallel microprocessor port for device control
Programmable noise suppression
External Tone Input
Pin selectable A/ -Law format
Low power CMOS technology
Available in 24 Pin PDIP and SOIC packages
Digital PBX / KTS
Conference bridges
Digital C.O. switches
RESET
Serial-to-Parallel
Conversion
PCM Mode
Linear
/A-Law
Control
to
A/
Attenuation/Noise Suppression
Cki
Timebase
F0i
Figure 1 - Functional Block Diagram
Cko
Channel RAM
PCM Tone
Generator
TF
Adder
and
Description
The MT8924 is designed to provide conference call
capability in digital switching systems. It allows up to
10 independent conferences to be set for up to 32
PCM voice channels.
A/ -Law companded data from the PCM input port is
converted to linear format, processed by a dedicated
arithmetic unit, re-converted to companded format
and then sent to the PCM output port.The PCM
output signal contains all the information of each
channel connected in conference except its own.
Programmable attenuation and noise suppression
are provided for channels connected in conference
or transparent mode. Additionally, an input for an
external tone is featured that can be used as a signal
to indicate to connected parties that they are on a
conference call.
TD
Overflow
MT8924AE
MT8924AS
PCM Conference Circuit (PCC)
OS
RD
Ordering Information
WR
0 C to +70 C
Preliminary Information
Control
Parallel-to-Serial
D0-D7
24 Pin Plastic DIP (600 mil)
24 Pin SOIC
Conversion
ISSUE 1
Linear
/A-Law
to
CS
C/D
MT8924
April 1994
DSTo
8-3

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MT8924AS Summary of contents

Page 1

... PCM Mode Control RESET Cki A/ PCM Conference Circuit (PCC) MT8924AE MT8924AS Description The MT8924 is designed to provide conference call capability in digital switching systems. It allows independent conferences to be set for PCM voice channels. A/ -Law companded data from the PCM input port is ...

Page 2

MT8924 Pin Description Pin # Name 1 TD Tone Duration (Input). When TD is High, a PCM-coded tone is sent out to all channels of the enabled conferences instead of PCM data latched by frame pulse F0i so ...

Page 3

Preliminary Information Pin Description (continued) Pin # Name 19 F0i Frame Pulse (Input). This kHz active low input used for frame synchronization of the PCM bit stream. The first falling edge of Cki following the falling edge ...

Page 4

MT8924 A-Law -Law Table 1 - PCM Noise Suppression Threshold Levels Overflow Detection / Input Channel Attenuation If the sum of the channels involved in one conference exceeds the full scale value of the accumulator, an overflow condition is generated ...

Page 5

Preliminary Information Noise Suppression When noise suppression is enabled for a specific input channel then the PCM bytes for this channel, when below the selected threshold level, are converted to PCM bytes corresponding to the minimum PCM code level before ...

Page 6

MT8924 control byte. The data byte contains the number of the channel to be disconnected. The second byte contains the opcode (D0-D3). One frame pulse must pass between disconnection reconnection of the same channel. Instruction 4 : Overflow Status Monitoring ...

Page 7

Preliminary Information Instruction 1 : Channel Connection in Conference Mode Control Signals Conference Start Bit P3-P0: Conference Number (1-10) ...

Page 8

MT8924 Instruction 5 : PCM Operating Mode Selection Control Signals Extra bit insertion (active when E= F0: PCM byte format selection (see Table ...

Page 9

Preliminary Information Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin 4 Storage Temperature 5 Power Dissipation (plastic package) * Exceeding these figures may cause permanent damage. Functional operation under ...

Page 10

MT8924 AC Electrical Characteristics - Clocked Timing* Characteristics 1 Clock period 2 Clock low level width 3 Clock high level width 4 Clock rise time 5 Clock fall time 6 Sync. low setup time 7 Sync. low level hold time ...

Page 11

Preliminary Information AC Electrical Characteristics - PCM Timing* Characteristics 1 Input PCM setup time 2 Input PCM hold time 3 Output PCM propagation delay *All AC characteristics are valid 250 s after V resistor. **With Extra Bit Insert operating mode ...

Page 12

MT8924 AC Electrical Characteristics - Write Timing Characteristics 1 Write Pulse low width 2 Write Pulse high width 3 Repetition Interval between active Write Pulses 4 Read high setup time to active Write Pulse 5 Read high hold time from ...

Page 13

Preliminary Information AC Electrical Characteristics - Read Timing Characteristics 1 Read Pulse low width 2 Read Pulse high width 3 Repetition Interval between active Read Pulses 4 Write high setup time to active Read Pulse 5 Write high hold time ...

Page 14

MT8924 Extra Bit Cki t PDEC Cko F0i Figure 10 - CKo Timing with Extra Bit Insertion Mode Channel N-1 Cki OS Figure Timing with Output PCM Channel belonging to a Conference in Overflow 8-16 Preliminary Information ...

Page 15

... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...

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