MT8924 Zarlink Semiconductor, MT8924 Datasheet
MT8924
Available stocks
Related parts for MT8924
MT8924 Summary of contents
Page 1
This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
Page 2
... A/ PCM Conference Circuit (PCC) MT8924AE MT8924AS Description The MT8924 is designed to provide conference call capability in digital switching systems. It allows independent conferences to be set for PCM voice channels. A/ -Law companded data from the PCM input port is converted to linear format, processed by a dedicated arithmetic unit, re-converted to companded format and then sent to the PCM output port ...
Page 3
... MT8924 Pin Description Pin # Name 1 TD Tone Duration (Input). When TD is High, a PCM-coded tone is sent out to all channels of the enabled conferences instead of PCM data latched by frame pulse F0i so that all channels have the same tone during the same frame number. When TD is Low, normal operation is enabled ...
Page 4
... MT898x series, or the MT9080, MT9085 combination). Normally the signal on this pin is identical to Cki. When Extra bit operating mode is selected (see Instruction 5), the first two cycles of the master clock are suppressed (see Figure 10). This feature allows the MT8924 to operate in 1544 kbit/s systems. ...
Page 5
... MT8924 A-Law -Law Table 1 - PCM Noise Suppression Threshold Levels Overflow Detection / Input Channel Attenuation If the sum of the channels involved in one conference exceeds the full scale value of the accumulator, an overflow condition is generated which can be monitored specifically by reading the status of the overfl ...
Page 6
... Cki. When operating with the extra bit selection, through Instruction 5, Cko is low for two clock periods, which allows operation of the MT8924 with the 1.544 MHz PCM frame format (see Figure 10). Transparent Mode The MT8924 can operate in transparent mode. In this case the PCM input (DSTi) is passed unmodifi ...
Page 7
... MT8924 control byte. The data byte contains the number of the channel to be disconnected. The second byte contains the opcode (D0-D3). One frame pulse must pass between disconnection reconnection of the same channel. Instruction 4 : Overflow Status Monitoring This function extracts overflow status information on all existing conferences and transfers it to the microprocessor data bus ...
Page 8
... MT8924 Comments D0 P0 Conference Number C0 PCM Channel Number and Insertion Tone control 1 Opcode, Attenuation, and Noise Suppression control Channel Noise Suppression A-Law -Law no noise suppression 9/4096 9/8159 16/4096 16/8159 32/4096 32/8159 ...
Page 9
... MT8924 Instruction 5 : PCM Operating Mode Selection Control Signals Extra bit insertion (active when E= F0: PCM byte format selection (see Table bit inverted 01 = even bit (B0, B2, B4, B6) inverted 10 = odd bit (B1, B3, B5) inverted 11 = all bits (B0, B1, B2, B3, B4, B5, B6) inverted ...
Page 10
... and C4i have been applied. DD Sym Min Typ Max I MT8924 Min Max Units - 150 C 500 mW Max Units Test Conditions 5. for 400mv noise DD margin ...
Page 11
... MT8924 AC Electrical Characteristics - Clocked Timing* Characteristics 1 Clock period 2 Clock low level width 3 Clock high level width 4 Clock rise time 5 Clock fall time 6 Sync. low setup time 7 Sync. low level hold time 8 Sync. high setup time 9 Sync. high width 10 OS propagation delay from rising ...
Page 12
... SHRES t t WHRES CK and the clock have been applied the max. capacitive load and SLRES t HLRES t SHRES t WHRES Figure 7 - Reset Timing MT8924 =5V5%) DD Max Units Test Conditions ns ns 125 ns C =150pF 2.048MHz mode ** s the test pull up i ...
Page 13
... MT8924 AC Electrical Characteristics - Write Timing Characteristics 1 Write Pulse low width 2 Write Pulse high width 3 Repetition Interval between active Write Pulses 4 Read high setup time to active Write Pulse 5 Read high hold time from active Write Pulse 6 Write Pulse rise time 7 Write Pulse fall time ...
Page 14
... HCDRD t PDD WHRD WLRD t FRD t REPRD t HHWR t SHCSRD t HLCSRD t HCDRD PDD Figure 9 - Read Timing Characteristics MT8924 =5V5%) DD Max Units Test Conditions Active case ns Active case ns Active case ns Active case ns ns 120 ns Read; C ...
Page 15
... MT8924 Extra Bit Cki t PDEC Cko F0i Figure 10 - CKo Timing with Extra Bit Insertion Mode Channel N-1 Cki OS Figure Timing with Output PCM Channel belonging to a Conference in Overflow 8-16 Preliminary Information Bit 0 Channel 0 Channel N Bit 1 Channel 0 Channel N+1 ...
Page 16
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...