MT8910 Zarlink Semiconductor, MT8910 Datasheet - Page 11

• Manufacturer Part Number: MT8910
• Description: Digital Subscriber Line Interface Circuit
• Manufacturer: Zarlink Semiconductor

MT8910-1
the superframe position. This function can also be
activated in software (LT mode only) through a bit in
Control Register 1 (TxSFB). The transition of this bit
from a 1 to a 0 will reset the superframe counter, and
the beginning of the transmitted superframe will be
referenced to the ST-BUS frame after the frame in
which the transition in the TxSFB bit occurred.
In the NT mode, the SFb pin is an output which
generates an active low signal at the boundary of the
transmit superframe. Since the SFb is referenced to
the receive time base, SFb is only valid after
9-12
CDSTo
CDSTi
DSTo
F0od
DSTi
DSTo
F0od
C4b
F0b
DSTi
F0b
C4b
Reserved
Reserved
B
C
B
C
7
7
7
7
D
D
0
0
B
C
B
C
6
6
6
6
D
D
Channel Time 0
1
1
D-Channel
B
C
B
C
5
5
5
5
Channel Time 0
Figure 8 - ST-BUS Channel Assignments in Single Port Mode
3.9 sec
B
C
B
C
Figure 9 - ST-BUS Channel Assignment in Dual Port Mode
4
4
4
4
B
C
B
C
3
3
3
3
B
C
B
C
62.5 sec
C
C
2
2
2
2
7
7
Channel Time 1
C
C
B
C
B
C
6
6
1
1
1
1
C-Channel
B
C
B
C
0
0
0
0
C
C
1
1
C
C
125 sec
0
0
15.6 sec
B
B
7
7
Channel Time 2
B
B
superframe synchronization has been achieved. In
the NT mode, the TxSFB bit is ignored since the
transmit superframe has a fixed phase relationship
with respect to the received superframe.
The MT8910-1 has two possible system port
configurations; single port mode or dual port mode.
In the single port mode, the MT8910-1 uses the first
four timeslots of the DSTi and DSTo data streams
(as shown in Figure 8).
allocated to the D-channel, ST-BUS Channel 1 to the
C-channel, while ST-BUS Channel 2 and 3 are
6
6
B1-Channel
D
D
B
B
7
0
7
0
B
B
D
D
B
B
1
1
1
1
6
6
B
B
0
0
B
B
5
5
B
B
Channel Time 16
7
7
B
B
B
B
Channel Time 3
4
4
6
6
B2-Channel
B
B
3
3
B
B
2
2
B
B
1
1
ST-BUS Channel 0 is
B
B
B
B
1
1
0
0
B
B
0
0
B
C
B
C
D
D
7
7
7
7
0
0