MT8910 Zarlink Semiconductor, MT8910 Datasheet
MT8910
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MT8910 Summary of contents
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This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
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... DSLIC to meet the loop length requirements of the digital subscriber loops at the U-interface over the entire non-loaded telephone loop plant. The MT8910-1 is compatible with the complete range of Mitel Semiconductor ISDN components through the use of the ST-BUS interface. Scrambler & ...
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... MT8910 Lout- Lin Lout+ Lin- 26 AVSS 3 VRef 25 TSTin 4 VBias 5 24 CDSTi AVDD 23 DSTi VSS VDD 7 DSTo 21 8 MRST 20 CDSTo 9 OSC1 19 F0od OSC2 10 TSTout 18 F0b 11 MS0 17 12 C4b MS1 16 13 SFb NT/LT 15 TSTen 14 28 PIN PDIP Pin Description Pin # Name ...
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... OSC2 Oscillator Output. When the MT8910-1 operates with an External Clock (typically LT mode) connect OSC2 to the output of an external inverter providing a 10.24 MHz 5ppm clock (see “10.24 MHz Clock Interface" section). When operating with a crystal (typically NT mode) connect one lead of the fundamental mode parallel resonator crystal (10 ...
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... DSP hardware. Since a digital transversal echo canceller gives a linear representation of the echo, the MT8910-1 also has a non-linear echo canceller which works in parallel with the transversal filter to compensate for non-linearities in the transmit path and the passive line termination. In addition, a ...
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... SW and ISW during the proper time interval MT8910 for LT -18 - for NT is modulo two summation) As such, the frame/superframe 2 quaternary symbols (quats) with ...
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... MT8910-1 Superframe Frame 1 Frame 2 Frame Information B11 B12 B13 B14 B15 B16 B17 B18 B21 B22 B23 B24 B25 B26 B27 B28 Channels Corresponding ST-BUS Basic Frame Synchronization (BFS) is achieved using the algorithm shown in Figure 5. The DSLIC searches for the sync word or the inverted sync word within the received data stream ...
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... EC Training Expiry of T0 Tx-SL1 EC Converged Framing Expiry of T0 Tx-SL2 ST.T3 SFS STP.T0 1 Active BFS Lost > 480ms Tx-SL3 or LDR ST.T3 1 Note : Loss of received signal will result in loss of sync. MT8910-1 All (Loss of signal (Loss of signal and and LDR) or Expiry of T3 LDR), ST.T2 STP.T3 Pending Deact. Tx-SL0 9-9 ...
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... MT8910-1 • TL kHz activation tone sourced by the LT which is generated by sending a continuous pattern of four +3 symbols followed by four -3 symbols. • SL0: SL0 signal condition generated from the LT. • SL1 generated signal consisting of a framed (but not superframed), scrambled 2B1Q signal which carries all 1s in the B-, D- and M-channels. This signal is used to train the LT’ ...
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... The I/O configuration of these pins is controlled by the mode of operation (LT or NT). In the LT mode, these timing signals must be supplied from an external source and the MT8910-1 will in turn uses these timing signals to transfer information to and from the line port or the ST-BUS port. In the ...
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... The MT8910-1 has two possible system port configurations; single port mode or dual port mode. In the single port mode, the MT8910-1 uses the first four timeslots of the DSTi and DSTo data streams (as shown in Figure 8). allocated to the D-channel, ST-BUS Channel 1 to the ...
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... B1 and B2 channels, respectively. In this mode, the CDSTi and CDSTo streams are not used. In the dual port mode, the MT8910-1 uses both the DSTi/DSTo streams as well as the CDSTi/ CDSTo streams to allow the separation of the data and control. The two B-channels are routed through the DSTi/DSTo streams and the C- and D-channels are routed through the CDSTi/CDSTo streams ...
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... MT8910-1 Bit 2 of Control Register 1, START/STOP, provides a mechanism to allow the user to initiate a line activation or deactivation. This bit is edge sensitive with a low to high transition requesting an activation, and a high to low transition deactivation. The activation and deactivation procedure will follow the protocol defined in the ANSI T1 ...
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... Control Register Select 1 and 0. Must be set respectively to address Control Register 2. 1 The ST-BUS incoming data is still output on the line if the MT8910-1 is activated. Supported in both SINGLE and DUAL port modes. 2 The incoming data from the line is still output on to the ST-BUS. The other incoming channels on the ST-BUS are still output on to the line if the device is activated ...
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... MT8910-1 Control Register 3 Setting CRS1 and CRS0 respectively, routes the input C-channel to Control Register 3, allowing access to the transmit M-bits as shown in Table 4. The transmit M-channel kbit/s maintenance channel which may carry the EOC messages (with overhead) as specified in T1.601-1988. Except for the CRC bits, the M-bits are treated as a transparent data channel through the DSLIC ...
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... Bit 0 of Status Register 1, CRCERR, indicates the state of the CRC check. A logic high on this bit states that the CRC check calculated by the MT8910-1 did not correspond to the CRC bits received in the M-channel. This bit will only be updated once every superframe. bit 7 ...
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... MT8910-1 bit 7 bit 6 SRID1 SRID0 Bit Name 7,6 SRID1, SRID0 Status Register ID. Always reads 1, 0, respectively, when Status Register 3 is output. 5,4,3, RPA4-RPA0 Receive Pulse Amplitude bits (see Note 1). 2,1 RPA4 - RPA0 ...
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... M5 and M6 carry the results of a CRC calculation (refer to Table 9). All bits except these CRC bits are treated as a transparent channel to the MT8910-1. The 12 bit cyclical redundancy check is computed using the generator polynomial ...
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... This requires the output impedance of the inverter to be high for minimizing the power consumption of the MT8910-1. When OSC1 is used as an input for an external clock (typically in LT mode), the high output impedance of the inverter coupled with any stray ...
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... Figures 11 and 12. receives all its timing from the system including the C4b, F0b and a frequency-locked 10.24 MHz master clock. In Figure 12, the MT8910-1 is configured in the NT mode which implies that all timing signals including the F0b, C4b and SFb are being sourced from the MT8910-1. ...
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... Figure 12 - Typical Connections for NT Mode (Single Port) Passive Line Termination Network (PLT) The termination network is an all passive circuit which allows the MT8910-1 to interface to the DSL line through a line pulse transformer. The passive line termination consists of three blocks which includes a hybrid network, a compensator circuit and a line pulse transformer (refer to Figures 13 and 14) ...
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... XFM XFM 1 30 TURNS RATIO 1:1.3 7 RESISTANCE R = 5-8 3 2-12 6 INDUCTANCE Leakage Inductance (Sec. Short Circuit) < kHz. LONGT. BAL kHz 6 4-160 kHz 12 MT8910-1 10 10% 5.5 mH Power 1.5 F Feed/Extract 5 10% min 63 dB min 58 dB 9-23 ...
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... MT8910-1 Absolute Maximum Ratings Parameters 1 Supply Voltage 2 Voltage on any I/O pin 3 Current on any I/O pin 4 Storage Temperature 5 Package Power Dissipation Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Note 1: Except for out+ and L out- . ...
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... External Clock Timing (Ref. Figure 15) ‡ Sym Min Typ Max 1/t 10.24 MCF OCH t MCF t 10 OCT t -15 +15 JC MT8910-1 ) unless otherwise stated. SS Max Units Test Conditions V Relative minimum Relative to V Bias minimum (see Note =10mA OH ...
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... MT8910-1 BIT 0, CHANNEL 31 t FPW V IH F0b FPS t FPH V IH C4b SFS V IH SFb F0od DSTi/ CDSTi DZA V OH DSTo/ CDSTo Electrical Characteristics Characteristics 1 F0b Input Pulse Width 2 Frame Pulse (F0b) Setup Time ...
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... SFW t 60 DFD t 1 DFW t 30 SIS t 50 SIH t 120 DAA t 120 DZA t 120 DAZ MT8910 DFD DFD t DFW t t DAA DAZ Units Test Conditions cycles C =150 pF, C4b cycles L ns 150 pF (see Note 3) ns 150 pF ns 150 pF ns 150 pF (see Note 1) ...
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... MT8910-1 Notes: 9-28 ...
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